SAM3N4C Atmel Corporation, SAM3N4C Datasheet - Page 343

• Manufacturer Part Number: SAM3N4C
• Manufacturer: Atmel Corporation

Specifications of SAM3N4C

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.5
24.6
24.7
11011A–ATARM–04-Oct-10
Processor Clock Controller
SysTick Clock
Peripheral Clock Controller
Figure 24-2. Master Clock Controller
The PMC features a Processor Clock Controller (HCLK) that implements the Processor Sleep
Mode. The Processor Clock can be disabled by executing the WFI (WaitForInterrupt) or the
WFE (WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast Startup
Mode Register (PMC_FSMR).
The Processor Clock HCLK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Sleep Mode is achieved by disabling the Processor Clock,
which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the
product.
When Processor Sleep Mode is entered, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
The SysTick calibration value is fixed at 6000 which allows the generation of a time base of 1 ms
with SysTick clock at 6 MHz (max HCLK/8).
The Power Management Controller controls the clocks of each embedded peripheral by means
of the Peripheral Clock Controller. The user can individually enable and disable the Clock on the
peripherals.
The user can also enable and disable these clocks by writing Peripheral Clock Enable
(PMC_PCER) and Peripheral Clock Disable (PMC_PCDR) registers. The status of the periph-
eral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR).
When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are
automatically disabled after a reset.
In order to stop a peripheral, it is recommended that the system software wait until the peripheral
has executed its last programmed operation before disabling the clock. This is to avoid data cor-
ruption or erroneous behavior of the system.
The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR and
PMC_PCSR) is the Peripheral Identifier defined at the product level. The bit number corre-
sponds to the interrupt source number assigned to the peripheral.
MAINCK
PLLCK
SLCK
PMC_MCKR
CSS
Master Clock
PMC_MCKR
Prescaler
PRES
MCK
To the Processor
Clock Controller (PCK)
SAM3N
343