SAM7S256 Atmel Corporation, SAM7S256 Datasheet - Page 162
SAM7S256
Manufacturer Part Number
SAM7S256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S256
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Instruction Cycle Timings
6.13
6-20
CP
status
ready
not ready
Coprocessor data operation
Cycle
1
1
2
•
b
Address
pc+8
pc+12
pc+8
pc+8
pc+8
pc+8
pc+12
A coprocessor data operation is a request from the core for the coprocessor to initiate
some action. The action does not have to be completed for some time, but the
coprocessor must commit to doing it before driving CPB LOW.
If the coprocessor is not capable of performing the requested task, it must leave CPA
and CPB HIGH. If it can do the task, but cannot commit right now, it must drive CPA
LOW but leave CPB HIGH until it can commit. The core busy-waits until CPB goes
LOW.
The cycle timings are listed in Table 6-16 where:
•
Coprocessor data operations are not available in Thumb state.
b represents the busy cycles.
Note
nRW
0
0
0
0
0
Copyright © 1994-2001. All rights reserved.
Table 6-16 Coprocessor data operation instruction cycle operations
MAS
[1:0]
2
2
2
2
2
Data
(pc+8)
(pc+8)
-
-
-
nMREQ
0
1
1
1
0
SEQ
0
0
0
0
0
nOPC
0
0
1
1
1
nCPI
0
0
0
0
0
ARM DDI 0029G
CPA
0
0
0
0
0
CPB
0
1
1
1
0
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