SAM7S256 Atmel Corporation, SAM7S256 Datasheet - Page 212
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SAM7S256
Manufacturer Part Number
SAM7S256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S256
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Signal Description
A-6
Name
DOUT[31:0]
Data output bus
DRIVEBS
Boundary scan cell enable
ECAPCLK
EXTEST capture clock
ECAPCLKBS
EXTEST capture clock for
boundary-scan
ECLK
External clock output
EXTERN0
External input 0
EXTERN1
External input 1
HIGHZ
High impedance
ICAPCLKBS
INTEST capture clock
Copyright © 1994-2001. All rights reserved.
Type
O8
O4
O4
O4
O4
IC
IC
O4
O4
Description
Unidirectional bus used to transfer data from the processor to the
memory system.
This bus is only used when BUSEN is HIGH. Otherwise it is driven to a
value of zero.
During write cycles the output data becomes valid while MCLK is LOW,
and remains valid until after the falling edge of MCLK.
Controls the multiplexors in the scan cells of an external boundary-scan
chain.
This must be left unconnected, if an external boundary-scan chain is not
connected.
Only used on the ARM7TDMI test chip, and must otherwise be left
unconnected.
Used to capture the device inputs of an external boundary-scan chain
during EXTEST.
When scan chain 3 is selected, the current instruction is EXTEST and the
TAP controller state machine is in the CAPTURE- DR state, then this
signal is a pulse equal in width to TCK2.
This must be left unconnected, if an external boundary-scan chain is not
connected.
In normal operation, this is simply MCLK, optionally stretched with
nWAIT, exported from the core. When the core is being debugged, this
is DCLK, which is generated internally from TCK.
This is connected to the EmbeddedICE Logic and allows breakpoints and
watchpoints to be dependent on an external condition.
This is connected to the EmbeddedICE Logic and allows breakpoints and
watchpoints to be dependent on an external condition.
When the HIGHZ instruction has been loaded into the TAP controller
this signal is HIGH.
See Appendix B Debug in Depth for details.
This is used to capture the device outputs in an external boundary-scan
chain during INTEST.
This must be left unconnected, if an external boundary-scan chain is not
connected.
Table A-3 Signal Descriptions (continued)
ARM DDI 0029G
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