SAM7S256 Atmel Corporation, SAM7S256 Datasheet - Page 50
SAM7S256
Manufacturer Part Number
SAM7S256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S256
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Programmer’s Model
2.3
2.3.1
2-4
31
Memory formats
Little-endian
Byte at address A+3
Halfword at address A+2
The ARM7TDMI processor views memory as a linear collection of bytes numbered in
ascending order from zero. For example:
•
•
The ARM7TDMI processor is bi-endian and can treat words in memory as being stored
in either:
•
•
Little-endian is traditionally the default format for ARM processors.
The endian format of a CPU dictates where the most significant byte or digits must be
placed in a word. Because numbers are calculated by the CPU starting with the least
significant digits, little-endian numbers are already set up for the processing order.
Endian configuration has no relevance unless data is stored as words and then accessed
in smaller sized quantities (halfwords or bytes).
In little-endian format, the lowest addressed byte in a word is considered the
least-significant byte of the word and the highest addressed byte is the most significant.
So the byte at address 0 of the memory system connects to data lines 7 through 0.
For a word-aligned address A, Figure 2-1 shows how the word at address A, the
halfword at addresses A and A+2, and the bytes at addresses A, A+1, A+2, and A+3
map on to each other when the core is configured as little-endian.
24 23
bytes zero to three hold the first stored word
bytes four to seven hold the second stored word.
Little-endian on page 2-4.
Big-Endian on page 2-5
Note
Byte at address A+2
Figure 2-1 LIttle-endian addresses of bytes and halfwords within words
Copyright © 1994-2001. All rights reserved.
Word at address A
16 15
Byte at address A+1
Halfword at address A
8 7
Byte at address A
ARM DDI 0029G
0
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