SAM7S256 Atmel Corporation, SAM7S256 Datasheet - Page 260
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SAM7S256
Manufacturer Part Number
SAM7S256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7S256
Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
55 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Debug in Depth
B.12.2 Using the mask registers
B.12.3 The control registers
B-42
ENABLE
The data to be written is shifted into the 32-bit data field. The address of the register is
shifted into the 5-bit address field. A 1 is shifted into the read/write bit.
A register is read by shifting its address into the address field and by shifting a 0 into
the read/write bit. The 32-bit data field is ignored.
The register addresses are shown in Table B-5 on page B-40.
A read or write actually takes place when the TAP controller enters the UPDATE-DR
state.
For each value register in a register pair, there is a mask register of the same format.
Setting a bit to 1 in the mask register has the effect of making the corresponding bit in
the value register disregarded in the comparison.
For example, when a watchpoint is required on a particular memory location, but the
data value is irrelevant, the data mask register can be programmed to
set to 1, to ignore the entire data bus field.
The mask is an XNOR mask rather than a conventional AND mask. When a mask bit is
set to 1, the comparator for that bit position always matches, irrespective of the value
register or the input value.
Setting the mask bit to 0 means that the comparator matches only if the input value
matches the value programmed into the value register.
The control value and control mask registers are mapped identically in the lower eight
bits, as shown in Figure B-8 on page B-42.
Bit 8 of the control value register is the ENABLE bit and cannot be masked.
8
Note
Note
RANGE
Copyright © 1994-2001. All rights reserved.
7
CHAIN
6
EXTERN
Figure B-8 Watchpoint control value and mask format
5
nTRANS
4
nOPC
3
MAS[1]
2
MAS[0]
1
ARM DDI 0029G
, all bits
nRW
0
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