SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 133

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

5.4.2
ARM DDI 0029G
Clock switch during test
When serial test patterns are being applied to the ARM7TDMI core through the JTAG
interface, the processor must be clocked using DCLK, MCLK must be held LOW.
Entry into test is less automatic than debug and you must take care to prevent spurious
clocking on the way into test.
The TAP controller can now be used to serially test the processor. If scan chain 0 and
INTEST are selected, DCLK is generated while the state machine is in the
RUN-TEST/IDLE state. During EXTEST, DCLK is not generated.
On exit from test, RESTART must be selected as the TAP controller instruction. When
this is done, MCLK can be resumed. After INTEST testing, you must take care to
ensure that the core is in a sensible state before reverting to normal operation. The safest
ways to do this is are by using one of the following:
•
•
select RESTART, then cause a system reset
insert
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into the instruction pipeline before reverting.
Debug Interface
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