SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 77

• Manufacturer Part Number: SAM7SE256
• Manufacturer: Atmel Corporation

Specifications of SAM7SE256

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 48 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 88
• Ext Interrupts: 88
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

3.3.3
ARM DDI 0029G
Internal cycles
Burst type
Word read
Word write
Halfword read
The possible burst types are listed in Table 3-2.
All accesses in a burst are of the same data width, direction, and protection type. For
more details, see Addressing signals on page 3-11.
Memory systems can often respond faster to a sequential access and can require a
shorter access time compared to a nonsequential access. An example of a burst access
is shown in Figure 3-3.
During an internal cycle, the ARM7TDMI processor does not require a memory access,
as an internal function is being performed, and no useful prefetching can be performed
at the same time.
nMREQ
D[31:0]
A[31:0]
MCLK
nRAS
nCAS
SEQ
Copyright © 1994-2001. All rights reserved.
Address increment
4 bytes
4 bytes
2 bytes
N-cycle
Cause
ARM7TDMIcore code fetches, or LDM instruction
STM instruction
Thumb code fetches
a
Figure 3-3 Sequential access cycles
a+4
S-cycle
Table 3-2 Burst types
Memory Interface
a+8
S-cycle
a+12
3-7