SAM7SE256 Atmel Corporation, SAM7SE256 Datasheet - Page 74
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SAM7SE256
Manufacturer Part Number
SAM7SE256
Description
Manufacturer
Atmel Corporation
Specifications of SAM7SE256
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
48 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
88
Ext Interrupts
88
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Memory Interface
3.3
3-4
Bus cycle types
The ARM7TDMI processor bus interface is pipelined. This gives the maximum time for
a memory cycle to decode the address and respond to the access request:
•
•
A single memory cycle is shown in Figure 3-1.
The ARM7TDMI processor bus interface can perform four different types of bus cycle:
•
•
•
•
memory request signals are broadcast in the bus cycle ahead of the bus cycle to
which they refer
address class signals are broadcast half a clock cycle ahead of the bus cycle to
which they refer.
a nonsequential cycle requests a transfer to or from an address which is unrelated
to the address used in the preceding cycle
a sequential cycle requests a transfer to or from an address which is either the
same, one word, or one halfword greater than the address used in the preceding
cycle
an internal cycle does not require a transfer because it is performing an internal
function, and no useful prefetching can be performed at the same time
a coprocessor register transfer cycle uses the data bus to communicate with a
coprocessor, but does not require any action by the memory system.
Copyright © 1994-2001. All rights reserved.
nMREQ
D[31:0]
A[31:0]
MCLK
SEQ
APE
Figure 3-1 Simple memory cycle
ARM DDI 0029G
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