SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 100

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Baud Rate Generator
Figure 37. Baud Rate Generator
100
MCK/8
MCK
SCK
AT91X40 Series
USCLKS [0]
0
1
USCLKS [1]
0
1
The Baud Rate Generator provides the bit period clock (the Baud Rate clock) to both the
Receiver and the Transmitter.
The Baud Rate Generator can select between external and internal clock sources. The
external clock source is SCK. The internal clock sources can be either the master clock
(MCK) or the master clock divided by 8 (MCK/8).
Note:
When the USART is programmed to operate in Asynchronous Mode (SYNC = 0 in the
Mode Register US_MR), the selected clock is divided by 16 times the value (CD) written
in US_BRGR (Baud Rate Generator Register). If US_BRGR is set to 0, the Baud Rate
Clock is disabled.
When the USART is programmed to operate in Synchronous Mode (SYNC = 1) and the
selected clock is internal (USCLKS[1] = 0 in the Mode Register US_MR), the Baud Rate
Clock is the internal selected clock divided by the value written in US_BRGR. If
US_BRGR is set to 0, the Baud Rate Clock is disabled.
In Synchronous Mode with external clock selected (USCLKS[1] = 1), the clock is pro-
vided directly by the signal on the SCK pin. No division is active. The value written in
US_BRGR has no effect.
CLK
Baud Rate
Baud Rate
In all cases, if an external clock is used, the duration of each of its levels must be longer
than the system clock (MCK) period. The external clock frequency must be at least 2.5
times lower than the system clock.
16-bit Counter
CD
=
=
USCLKS [1]
SYNC
Selected Clock
Selected Clock
OUT
0
16 x CD
CD
CD
>1
1
0
0
1
Divide
by 16
SYNC
0
1
1354D–ATARM–08/02
Baud Rate
Clock