SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 75

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Interrupts
User Interface
1354D–ATARM–08/02
Each parallel I/O can be programmed to generate an interrupt when a level change
occurs. This is controlled by the PIO_IER (Interrupt Enable) and PIO_IDR (Interrupt Dis-
able) registers which enable/disable the I/O interrupt by setting/clearing the
corresponding bit in the PIO_IMR. When a change in level occurs, the corresponding bit
in the PIO_ISR (Interrupt Status) is set whether the pin is used as a PIO or a peripheral
and whether it is defined as input or output. If the corresponding interrupt in PIO_IMR
(Interrupt Mask) is enabled, the PIO interrupt is asserted.
When PIO_ISR is read, the register is automatically cleared.
Each individual I/O is associated with a bit position in the Parallel I/O user interface reg-
isters. Each of these registers are 32 bits wide. If a parallel I/O line is not defined, writing
to the corresponding bits has no effect. Undefined bits read zero.
AT91X40 Series
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