SAM9263 Atmel Corporation, SAM9263 Datasheet
SAM9263
Specifications of SAM9263
Related parts for SAM9263
SAM9263 Summary of contents
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... Periodic Interval Timer, Watchdog Timer and Double Real-time Timer ® ® Thumb Processor ® ® Technology for Java Acceleration ™ AT91 ARM Thumb Microcontrollers AT91SAM9263 Summary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6249HS–ATARM–27-Jul-09 ...
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... Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • One Four-channel 16-bit PWM Controller (PWMC) • One Two-wire Interface (TWI) – Master Mode Support, All Two-wire Atmel AT91SAM9263 2 ™ Compliant ® Infrared Modulation/Demodulation, Manchester Encoding/Decoding ® ...
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... EBI0 and EBI1, capable of interfacing with a wide range of memory devices and an IDE hard disk. Two external buses pre- vent bottlenecks, thus guaranteeing maximum performance. The AT91SAM9263 embeds an LCD Controller supported by a Two D Graphics Controller and a 2-channel DMA Control- ler, and one Image Sensor Interface. It also integrates several standard peripherals, such as USART, SPI, TWI, Timer Counters, PWM Generators, Multimedia Card interface and one CAN Controller ...
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... AT91SAM9263 Block Diagram Figure 2-1. AT91SAM9263 Block Diagram AT91SAM9263 4 6249HS–ATARM–27-Jul-09 ...
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... Test Mode Select JTAGSEL JTAG Selection RTCK Return Test Clock 6249HS–ATARM–27-Jul-09 gives details on the signal name classified by peripheral. Power Supplies Clocks, Oscillators and PLLs Shutdown, Wakeup Logic ICE and JTAG AT91SAM9263 Active Type Level Comments Power 1.65V to 3.6V Power 1.65V to 3.6V Power 2.7V to 3.6V Power 1 ...
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... EBI0_NCS0 - EBI0_NCS5, Chip Select Lines EBI1_NCS0 - EBI1_NCS2 EBIx_NWR0 -EBIx_NWR3 Write Signal EBIx_NRD Read Signal EBIx_NWE Write Enable EBIx_NBS0 - EBIx_NBS3 Byte Mask Signal AT91SAM9263 6 Embedded Trace Module - ETM Output Output Output Output Reset/Test Debug Unit - DBGU Output Advanced Interrupt Controller - AIC PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE ...
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... Output Output SDRAM Controller Output Output Output Output Output Output Output Multimedia Card Interface Output I/O I/O I/O I/O I/O I/O Input Output Input Synchronous Serial Controller SSC Output Input AT91SAM9263 Active Level Comments Low Low Low Low Low Low Low Low Low High Low Low Low 7 ...
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... CAN Input CANTX CAN Output LCDD0 - LCDD23 LCD Data Bus LCDVSYNC LCD Vertical Synchronization LCDHSYNC LCD Horizontal Synchronization LCDDOTCK LCD Dot Clock LCDDEN LCD Data Enable LCDCC LCD Contrast Control AT91SAM9263 8 Type I/O I/O I/O I/O AC97 Controller - AC97C Input Output Output Input Timer/Counter - TC Input I/O ...
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... USB Host Port Analog Analog Analog Analog Image Sensor Interface - ISI Input Output Input Input Input AT91SAM9263 Active Level Comments MII only, REFCK in RMII MII only ETX0-ETX1 only in RMII MII only RXDV in MII, CRSDV in RMII ERX0-ERX1 only in RMII MII only MII only ...
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... Package and Pinout The AT91SAM9263 is available in a 324-ball TFBGA Green package mm, 0.8mm ball pitch. 4.1 324-ball TFBGA Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9263 Mechanical Character- istics” in the product datasheet. Figure 4-1. 324-ball TFBGA Pinout (Top View) ...
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... TFBGA Package Pinout Table 4-1. AT91SAM9263 Pinout for 324-ball TFBGA Package Pin Signal Name Pin A1 EBI0_D2 E10 A2 EBI0_SDCKE E11 A3 EBI0_NWE_NWR0 E12 A4 EBI0_NCS1_SDCS E13 A5 EBI0_A19 E14 A6 EBI0_A11 E15 A7 EBI0_A10 E16 A8 EBI0_A5 E17 A9 EBI0_A1_NBS2_NWR2 E18 A10 PD4 F1 A11 PC30 F2 A12 PC26 F3 A13 PC24 ...
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... Table 4-1. AT91SAM9263 Pinout for 324-ball TFBGA Package (Continued) Pin Signal Name Pin C15 PC3 H6 C16 GND H7 C17 VDDIOP0 H8 C18 HDPB H9 D1 EBI0_D10 H10 D2 EBI0_D3 H11 ( H12 D4 EBI0_D1 H13 D5 EBI0_A20 H14 D6 EBI0_A17_BA1 H15 D7 EBI0_A18 H16 D8 EBI0_A9 H17 D9 EBI0_A2 H18 D10 PD1 ...
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... Power Consumption The AT91SAM9263 consumes about 700 µA (worst case) of static current on VDDCORE at 25°C. This static current rises the temperature increases to 85°C. On VDDBU, the current does not exceed 3 µA @25°C, but can rise µA @85°C. An automatic switch to VDDCORE guarantees low power consumption on the battery when the sys- tem is on ...
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... This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables on 6.5 Shutdown Logic Pins The SHDN pin is a tri-state output only pin, which is driven by the Shutdown Controller. There is no internal pull-up. An external pull-up to VDDBU is needed and its value must be higher than 1 AT91SAM9263 14 Section 6.3. page 36 and following. ...
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... Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit 6249HS–ATARM–27-Jul-09 each quarter of the page system flexibility 32-bit data interface (Words) AT91SAM9263 15 ...
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... Allows Handling of Dynamic Exception Vectors 7.3 Matrix Masters The Bus Matrix of the AT91SAM9263 manages nine masters, thus each master can perform an access concurrently with others to an available slave peripheral or memory. Each master has its own decoder, which is defined specifically for each master. ...
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... Slave 3 Slave 4 Slave 5 Slave 6 6249HS–ATARM–27-Jul-09 List of Bus Matrix Slaves Internal ROM Internal 80 Kbyte SRAM Internal 16 Kbyte SRAM LCD Controller User Interface DMA Controller User Interface USB Host User Interface External Bus Interface 0 External Bus Interface 1 Peripheral Bridge AT91SAM9263 17 ...
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... Two for the AC97 Controller – One for each Multimedia Card Interface The Peripheral DMA Controller handles transfer requests from the channel according to the fol- lowing priorities (low to high priorities): – DBGU Transmit Channel – USART2 Transmit Channel AT91SAM9263 Two D ...
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... Programmable multiple transaction size for each channel – Support for cleanly disabling a channel without data loss 6249HS–ATARM–27-Jul-09 lists transfer. Writing a stream of data into non-contiguous fields in system memory. transfer programmed values at the end of a block transfer of block transfer in block chaining mode AT91SAM9263 19 ...
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... Eight Memory Map Decoder Inputs – Two 16-bit Counters – One 3-stage Sequencer – One 45-byte FIFO • IEEE1149.1 JTAG Boundary-scan on All Digital Pins AT91SAM9263 20 to control the flow of a DMA transfer in place of a hardware handshaking interface completion, Single/Multiple transaction completion or Error condition ™ ...
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... Memories Figure 8-1. AT91SAM9263 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI0 Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI0 Chip Select 1/ EBI0 SDRAMC 0x2FFF FFFF 0x3000 0000 EBI0 Chip Select 2 0x3FFF FFFF 0x4000 0000 EBI0 Chip Select 3/ ...
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... Internal 80 Kbyte Fast SRAM The AT91SAM9263 device embeds a high-speed 80 Kbyte SRAM. This internal SRAM is split into three areas. Its memory mapping is presented in • Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR ...
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... Kbyte blocks assignments (RB0 ITCM = 32 Kbytes ITCM = 16 Kbytes DTCM = 32 Kbytes DTCM = 32 Kbytes (1) AHB = 16 Kbytes AHB = 32 Kbytes RB1 RB0 RB3 RB2 AT91SAM9263 Table 8-2. This table provides the Internal SRAM A (ITCM) Size 16 Kbytes 32 Kbytes 64 Kbytes 48 Kbytes 48 Kbytes 32 Kbytes 32 Kbytes 16 Kbytes ...
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... When REMAP = 0, BMS allows the user to layout at address 0x0 either the ROM or an external memory. This is done via hardware at reset. Note: The AT91SAM9263 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect. ...
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... The external memories are accessed through the External Bus Interfaces 0 and 1. Each Chip Select line has a 256 Mbyte memory area assigned. Refer to 8.2.1 External Bus Interfaces The AT91SAM9263 features two External Bus Interfaces to offer more bandwidth to the system and to prevent bottlenecks while accessing external memories. 8.2.1.1 External Bus Interface 0 • Integrates three External Memory Controllers: – ...
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... SDRAM with 16- or 32-bit Data Path • Programming facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable AT91SAM9263 26 6249HS–ATARM–27-Jul-09 ...
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... ARM instruction set, as the Load/Store instructions have an indexing mode of ± 4 Kbytes. Figure 9-1 on page 28 Figure 8-1 on page 21 peripherals. 6249HS–ATARM–27-Jul-09 detected erroneous pages shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller AT91SAM9263 27 ...
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... System Controller Block Diagram Figure 9-1. AT91SAM9263 System Controller Block Diagram irq0-irq1 periph_irq[2..29] pit_irq rtt0_irq rtt1_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd debug periph_nreset SLCK debug proc_nreset NRST VDDCORE POR VDDCORE VDDBU VDDBU POR SLCK SLCK backup_nreset SLCK backup_nreset SLCK SHDN WKUP ...
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... Clock Generator XIN32 Slow Clock Oscillator XOUT32 XIN Main Oscillator XOUT PLL and PLLRCA Divider A PLL and PLLRCB Divider B Status Control Power Management Controller AT91SAM9263 Slow Clock SLCK Main Clock MAINCK PLLA Clock PLLACK PLLB Clock PLLBCK 29 ...
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... Includes a 12-bit Interval Overlay Counter • Real-time OS or Linux 9.7 Watchdog Timer • 16-bit key-protected Counter, programmable only once AT91SAM9263 30 frequency, processor stopped waiting for an interrupt AT91SAM9263 Power Management Controller Block Diagram Master Clock Controller SLCK Prescaler MAINCK PLLACK /1,/2,/4,...,/64 PLLBCK Programmable Clock Controller ...
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... Easy debugging by preventing automatic operations when protect models are • Fast Forcing – Permits redirecting any normal interrupt source on the Fast Interrupt of the 9.12 Debug Unit • Composed of two functions • Two-pin UART 6249HS–ATARM–27-Jul-09 oscillator Shutdown Controller enabled processor AT91SAM9263 31 ...
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... Multi-drive option enables driving in open drain – Programmable pull-up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write AT91SAM9263 32 Generator the ARM Processor’s ICE Interface ...
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... FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in 10.2 Identifiers Table 10-1 the peripheral interrupt with the Advanced Interrupt Controller and for the control of the periph- eral clock with the Power Management Controller. Table 10-1. AT91SAM9263 Peripheral Identifiers Peripheral ID Peripheral Mnemonic 0 AIC 1 SYSC 2 PIOA ...
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... Peripheral 19 disables the clock of the 3 channels. 10.3 Peripherals Signals Multiplexing on I/O Lines The AT91SAM9263 device features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions The multiplexing tables define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “ ...
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... PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. 6249HS–ATARM–27-Jul-09 AT91SAM9263 35 ...
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... PA20 MCI0_DB3 PA21 MCI1_CDB PA22 MCI1_DB0 PA23 MCI1_DB1 PA24 MCI1_DB2 PA25 MCI1_DB3 PA26 TXD0 PA27 RXD0 PA28 RTS0 PA29 CTS0 PA30 SCK0 PA31 DMARQ0 AT91SAM9263 36 Reset Power Peripheral B State Supply SPI0_MISO I/O VDDIOP0 SPI0_MOSI I/O VDDIOP0 SPI0_SPCK I/O VDDIOP0 SPI0_NPCS1 I/O VDDIOP0 SPI0_NPCS2 I/O VDDIOP0 SPI0_NPCS0 I/O ...
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... PCK1 I/O SPI0_NPCS3 I/O I/O I/O I/O I/O PCK1 I/O TIOA2 I/O TIOB2 I/O I/O I/O I/O I/O I/O DMARQ3 I/O I/O I/O PWM2 I/O TCLK0 I/O PWM3 I/O I/O I/O AT91SAM9263 Application Usage Power Supply Function Comments VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 ...
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... PC20 LCDD16 PC21 LCDD17 PC22 LCDD18 PC23 LCDD19 PC24 LCDD20 PC25 LCDD21 PC26 LCDD22 PC27 LCDD23 PC28 PWM0 PC29 PCK0 PC30 DRXD PC31 DTXD AT91SAM9263 38 Reset Power Peripheral B State Supply I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 PWM1 I/O VDDIOP0 LCDD3 I/O VDDIOP0 LCDD4 I/O VDDIOP0 LCDD5 I/O VDDIOP0 ...
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... TPK3 I/O TPK4 I/O TPK5 I/O TPK6 I/O TPK7 I/O TPK8 I/O TPK9 I/O TPK10 I/O TPK11 I/O TPK12 I/O TPK13 I/O TPK14 I/O TPK15 I/O AT91SAM9263 Application Usage Power Supply Function Comments VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 ...
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... PE18 PE19 PE20 PE21 ETXCK PE22 ECRS PE23 ETX0 PE24 ETX1 PE25 ERX0 PE26 ERX1 PE27 ERXER PE28 ETXEN PE29 EMDC PE30 EMDIO PE31 EF100 AT91SAM9263 40 Reset Power Peripheral B State Supply I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 TIOA1 I/O VDDIOP1 ...
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... Using USART2 prevents using EBI0’s NWAIT signal, Chip Select 4 and CompactFlash Chip Enable 2. Using USART1 prevents using EBI0’s Chip Select 5 and CompactFlash Chip Enable1. 10.4.7 NAND Flash Using the NAND Flash interface on EBI1 prevents using Ethernet MAC. 6249HS–ATARM–27-Jul-09 AT91SAM9263 41 ...
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... The chip select line may be left active to speed up transfers on the same device 10.5.2 Two-wire Interface • Master Mode only • Compatibility with standard two-wire serial memory • One, two or three bytes for slave address • Sequential read/write operations AT91SAM9263 42 peripherals Sensors and data per chip select 6249HS–ATARM–27-Jul-09 ...
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... Time Slot Assigner that can assign time slots to a channel • Channels support mono or stereo up to 20-bit sample length – Variable sampling rate AC97 Codec Interface (48 kHz and below) 6249HS–ATARM–27-Jul-09 AT91SAM9263 2 S, TDM Buses, Magnetic Card Reader, etc.) 43 ...
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... Each MCI has two slots, each supporting – One slot for one MultiMediaCard bus ( cards) or – One SD Memory Card • Support for stream, block and multi-block data read and write 10.5.9 CAN Controller • Fully compliant with 16-mailbox CAN 2.0A and 2.0B CAN Controllers AT91SAM9263 44 6249HS–ATARM–27-Jul-09 ...
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... Up to 24-bit single scan TFT interfaces supported • gray levels for mono STN and up to 4096 colors for color STN displays • bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN 6249HS–ATARM–27-Jul-09 AT91SAM9263 45 ...
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... Vertical and horizontal resolutions up to 2048 x 2048 • Preview Path up to 640*480 • Support for packed data formatting for YCbCr 4:2:2 formats • Preview scaler to generate smaller size image • Programmable frame capture rate AT91SAM9263 46 over this virtual frame buffer 6249HS–ATARM–27-Jul-09 ...
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... Device and 324-ball TFBGA Package Maximum Weight 572 Table 11-3. 324-ball TFBGA Package Characteristics Moisture Sensitivity Level Table 11-4. Package Reference JEDEC Drawing Reference JESD97 Classification This package respects the recommendations of the NEMI User Group. 6249HS–ATARM–27-Jul-09 AT91SAM9263 0.4 mm +/- 0.05 0.275 mm +/- 0. MO-210 e1 47 ...
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... AT91SAM9263 Ordering Information Table 12-1. AT91SAM9263 Ordering Information MLR A Ordering Code MLR B Ordering Code AT91SAM9263-CU AT91SAM9263B-CU AT91SAM9263 48 Package Package Type TFBGA 324 Green Temperature Operating Range Industrial -40°C to 85°C 6249HS–ATARM–27-Jul-09 ...
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... Section 10.5.8 ”Multimedia Card Section 8.2.1.1 ”External Bus Interface Section 8.2.1.1 ”External Bus Interface “Package and Pinout”, references to package are “324-TFBGA. Figure 9-3 ”AT91SAM9263 Power Management Controller Block Diagram” on page Figure 11-1 ”324-ball TFBGA Package Drawing” on page 6249HS–ATARM–27-Jul-09 ™ Section 10.4.2 “ETM ” ...
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... EMAC. 41, added Ethernet 10/100 MAC to the System Resource Multiplexing list of and Section 10.4.12 “Timers” on page Section 1. “Description” on page Section 12. “AT91SAM9263 Ordering Information” on page corrected package top view. 16, Table 7-2, “List of Bus Matrix 18. 42, removed 3 ...
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