SAM9263 Atmel Corporation, SAM9263 Datasheet
SAM9263
Specifications of SAM9263
Related parts for SAM9263
SAM9263 Summary of contents
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... Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit ® ® ARM Thumb Processor ® ® Technology for Java Acceleration ™ AT91SAM ARM-based Embedded MPU AT91SAM9263 6249I–ATARM–3-Oct-11 ...
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... Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • One Four-channel 16-bit PWM Controller (PWMC) • One Two-wire Interface (TWI) – Master Mode Support, All Two-wire Atmel AT91SAM9263 2 ™ Compliant ® Infrared Modulation/Demodulation, Manchester Encoding/Decoding ® ...
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... EBI0 and EBI1, capable of interfacing with a wide range of memory devices and an IDE hard disk. Two external buses pre- vent bottlenecks, thus guaranteeing maximum performance. The AT91SAM9263 embeds an LCD Controller supported by a Two D Graphics Controller and a 2-channel DMA Control- ler, and one Image Sensor Interface. It also integrates several standard peripherals, such as USART, SPI, TWI, Timer Counters, PWM Generators, Multimedia Card interface and one CAN Controller ...
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... AT91SAM9263 Block Diagram Figure 2-1. AT91SAM9263 Block Diagram AT91SAM9263 4 6249I–ATARM–3-Oct-11 ...
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... Test Mode Select JTAGSEL JTAG Selection RTCK Return Test Clock 6249I–ATARM–3-Oct-11 gives details on the signal name classified by peripheral. Power Supplies Clocks, Oscillators and PLLs Shutdown, Wakeup Logic ICE and JTAG AT91SAM9263 Active Type Level Comments Power 1.65V to 3.6V Power 1.65V to 3.6V Power 2.7V to 3.6V Power 1 ...
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... EBI0_NCS0 - EBI0_NCS5, Chip Select Lines EBI1_NCS0 - EBI1_NCS2 EBIx_NWR0 -EBIx_NWR3 Write Signal EBIx_NRD Read Signal EBIx_NWE Write Enable EBIx_NBS0 - EBIx_NBS3 Byte Mask Signal AT91SAM9263 6 Embedded Trace Module - ETM Output Output Output Output Reset/Test Debug Unit - DBGU Output Advanced Interrupt Controller - AIC PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE ...
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... Output Output SDRAM Controller Output Output Output Output Output Output Output Multimedia Card Interface Output I/O I/O I/O I/O I/O I/O Input Output Input Synchronous Serial Controller SSC Output Input AT91SAM9263 Active Level Comments Low Low Low Low Low Low Low Low Low High Low Low Low 7 ...
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... CAN Input CANTX CAN Output LCDD0 - LCDD23 LCD Data Bus LCDVSYNC LCD Vertical Synchronization LCDHSYNC LCD Horizontal Synchronization LCDDOTCK LCD Dot Clock LCDDEN LCD Data Enable LCDCC LCD Contrast Control AT91SAM9263 8 Type I/O I/O I/O I/O AC97 Controller - AC97C Input Output Output Input Timer/Counter - TC Input I/O ...
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... USB Host Port Analog Analog Analog Analog Image Sensor Interface - ISI Input Output Input Input Input AT91SAM9263 Active Level Comments MII only, REFCK in RMII MII only ETX0-ETX1 only in RMII MII only RXDV in MII, CRSDV in RMII ERX0-ERX1 only in RMII MII only MII only ...
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... Package and Pinout The AT91SAM9263 is available in a 324-ball TFBGA Green package mm, 0.8mm ball pitch. 4.1 324-ball TFBGA Package Outline Figure 4-1 A detailed mechanical description is given in the section “AT91SAM9263 Mechanical Character- istics” in the product datasheet. Figure 4-1. 324-ball TFBGA Pinout (Top View) ...
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... TFBGA Package Pinout Table 4-1. AT91SAM9263 Pinout for 324-ball TFBGA Package Pin Signal Name Pin A1 EBI0_D2 E10 A2 EBI0_SDCKE E11 A3 EBI0_NWE_NWR0 E12 A4 EBI0_NCS1_SDCS E13 A5 EBI0_A19 E14 A6 EBI0_A11 E15 A7 EBI0_A10 E16 A8 EBI0_A5 E17 A9 EBI0_A1_NBS2_NWR2 E18 A10 PD4 F1 A11 PC30 F2 A12 PC26 F3 A13 PC24 ...
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... Table 4-1. AT91SAM9263 Pinout for 324-ball TFBGA Package (Continued) Pin Signal Name Pin C15 PC3 H6 C16 GND H7 C17 VDDIOP0 H8 C18 HDPB H9 D1 EBI0_D10 H10 D2 EBI0_D3 H11 ( H12 D4 EBI0_D1 H13 D5 EBI0_A20 H14 D6 EBI0_A17_BA1 H15 D7 EBI0_A18 H16 D8 EBI0_A9 H17 D9 EBI0_A2 H18 D10 PD1 ...
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... Power Consumption The AT91SAM9263 consumes about 700 µA (worst case) of static current on VDDCORE at 25°C. This static current rises the temperature increases to 85°C. On VDDBU, the current does not exceed 3 µA @25°C, but can rise µA @85°C. An automatic switch to VDDCORE guarantees low power consumption on the battery when the sys- tem is on ...
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... This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables on 6.5 Shutdown Logic Pins The SHDN pin is a tri-state output only pin, which is driven by the Shutdown Controller. There is no internal pull-up. An external pull-up to VDDBU is needed and its value must be higher than 1 AT91SAM9263 14 Section 6.3. page 36 and following. ...
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... Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit 6249I–ATARM–3-Oct-11 each quarter of the page system flexibility 32-bit data interface (Words) AT91SAM9263 15 ...
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... Allows Handling of Dynamic Exception Vectors 7.3 Matrix Masters The Bus Matrix of the AT91SAM9263 manages nine masters, thus each master can perform an access concurrently with others to an available slave peripheral or memory. Each master has its own decoder, which is defined specifically for each master. ...
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... Slave 3 Slave 4 Slave 5 Slave 6 6249I–ATARM–3-Oct-11 List of Bus Matrix Slaves Internal ROM Internal 80 Kbyte SRAM Internal 16 Kbyte SRAM LCD Controller User Interface DMA Controller User Interface USB Host User Interface External Bus Interface 0 External Bus Interface 1 Peripheral Bridge AT91SAM9263 17 ...
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... Two for the AC97 Controller – One for each Multimedia Card Interface The Peripheral DMA Controller handles transfer requests from the channel according to the fol- lowing priorities (low to high priorities): – DBGU Transmit Channel – USART2 Transmit Channel AT91SAM9263 Two D ...
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... Programmable multiple transaction size for each channel – Support for cleanly disabling a channel without data loss 6249I–ATARM–3-Oct-11 lists transfer. Writing a stream of data into non-contiguous fields in system memory. transfer programmed values at the end of a block transfer of block transfer in block chaining mode AT91SAM9263 19 ...
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... Eight Memory Map Decoder Inputs – Two 16-bit Counters – One 3-stage Sequencer – One 45-byte FIFO • IEEE1149.1 JTAG Boundary-scan on All Digital Pins AT91SAM9263 20 to control the flow of a DMA transfer in place of a hardware handshaking interface completion, Single/Multiple transaction completion or Error condition ™ ...
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... Memories Figure 8-1. AT91SAM9263 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI0 Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI0 Chip Select 1/ EBI0 SDRAMC 0x2FFF FFFF 0x3000 0000 EBI0 Chip Select 2 0x3FFF FFFF 0x4000 0000 EBI0 Chip Select 3/ ...
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... Internal 80 Kbyte Fast SRAM The AT91SAM9263 device embeds a high-speed 80 Kbyte SRAM. This internal SRAM is split into three areas. Its memory mapping is presented in • Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR ...
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... Kbyte blocks assignments (RB0 ITCM = 32 Kbytes ITCM = 16 Kbytes DTCM = 32 Kbytes DTCM = 32 Kbytes (1) AHB = 16 Kbytes AHB = 32 Kbytes RB1 RB0 RB3 RB2 AT91SAM9263 Table 8-2. This table provides the Internal SRAM A (ITCM) Size 16 Kbytes 32 Kbytes 64 Kbytes 48 Kbytes 48 Kbytes 32 Kbytes 32 Kbytes 16 Kbytes ...
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... When REMAP = 0, BMS allows the user to layout at address 0x0 either the ROM or an external memory. This is done via hardware at reset. Note: The AT91SAM9263 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect. ...
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... The external memories are accessed through the External Bus Interfaces 0 and 1. Each Chip Select line has a 256 Mbyte memory area assigned. Refer to 8.2.1 External Bus Interfaces The AT91SAM9263 features two External Bus Interfaces to offer more bandwidth to the system and to prevent bottlenecks while accessing external memories. 8.2.1.1 External Bus Interface 0 • Integrates three External Memory Controllers: – ...
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... SDRAM with 16- or 32-bit Data Path • Programming facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable AT91SAM9263 26 6249I–ATARM–3-Oct-11 ...
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... ARM instruction set, as the Load/Store instructions have an indexing mode of ± 4 Kbytes. Figure 9-1 on page 28 Figure 8-1 on page 21 peripherals. 6249I–ATARM–3-Oct-11 detected erroneous pages shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller AT91SAM9263 27 ...
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... System Controller Block Diagram Figure 9-1. AT91SAM9263 System Controller Block Diagram irq0-irq1 periph_irq[2..29] pit_irq rtt0_irq rtt1_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset dbgu_rxd debug periph_nreset SLCK debug proc_nreset NRST VDDCORE POR VDDCORE VDDBU VDDBU POR SLCK SLCK backup_nreset SLCK backup_nreset SLCK SHDN WKUP ...
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... Clock Generator XIN32 Slow Clock Oscillator XOUT32 XIN Main Oscillator XOUT PLL and PLLRCA Divider A PLL and PLLRCB Divider B Status Control Power Management Controller AT91SAM9263 Slow Clock SLCK Main Clock MAINCK PLLA Clock PLLACK PLLB Clock PLLBCK 29 ...
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... Includes a 12-bit Interval Overlay Counter • Real-time OS or Linux 9.7 Watchdog Timer • 16-bit key-protected Counter, programmable only once AT91SAM9263 30 frequency, processor stopped waiting for an interrupt AT91SAM9263 Power Management Controller Block Diagram Master Clock Controller SLCK Prescaler MAINCK PLLACK /1,/2,/4,...,/64 PLLBCK Programmable Clock Controller ...
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... Easy debugging by preventing automatic operations when protect models are • Fast Forcing – Permits redirecting any normal interrupt source on the Fast Interrupt of the 9.12 Debug Unit • Composed of two functions • Two-pin UART 6249I–ATARM–3-Oct-11 oscillator Shutdown Controller enabled processor AT91SAM9263 31 ...
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... Multi-drive option enables driving in open drain – Programmable pull-up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write AT91SAM9263 32 Generator the ARM Processor’s ICE Interface ...
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... FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in 10.2 Identifiers Table 10-1 the peripheral interrupt with the Advanced Interrupt Controller and for the control of the periph- eral clock with the Power Management Controller. Table 10-1. AT91SAM9263 Peripheral Identifiers Peripheral ID Peripheral Mnemonic 0 AIC 1 SYSC 2 PIOA ...
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... Peripheral 19 disables the clock of the 3 channels. 10.3 Peripherals Signals Multiplexing on I/O Lines The AT91SAM9263 device features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions The multiplexing tables define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “ ...
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... PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. 6249I–ATARM–3-Oct-11 AT91SAM9263 35 ...
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... PA20 MCI0_DB3 PA21 MCI1_CDB PA22 MCI1_DB0 PA23 MCI1_DB1 PA24 MCI1_DB2 PA25 MCI1_DB3 PA26 TXD0 PA27 RXD0 PA28 RTS0 PA29 CTS0 PA30 SCK0 PA31 DMARQ0 AT91SAM9263 36 Reset Power Peripheral B State Supply SPI0_MISO I/O VDDIOP0 SPI0_MOSI I/O VDDIOP0 SPI0_SPCK I/O VDDIOP0 SPI0_NPCS1 I/O VDDIOP0 SPI0_NPCS2 I/O VDDIOP0 SPI0_NPCS0 I/O ...
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... PCK1 I/O SPI0_NPCS3 I/O I/O I/O I/O I/O PCK1 I/O TIOA2 I/O TIOB2 I/O I/O I/O I/O I/O I/O DMARQ3 I/O I/O I/O PWM2 I/O TCLK0 I/O PWM3 I/O I/O I/O AT91SAM9263 Application Usage Power Supply Function Comments VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 ...
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... PC20 LCDD16 PC21 LCDD17 PC22 LCDD18 PC23 LCDD19 PC24 LCDD20 PC25 LCDD21 PC26 LCDD22 PC27 LCDD23 PC28 PWM0 PC29 PCK0 PC30 DRXD PC31 DTXD AT91SAM9263 38 Reset Power Peripheral B State Supply I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 PWM1 I/O VDDIOP0 LCDD3 I/O VDDIOP0 LCDD4 I/O VDDIOP0 LCDD5 I/O VDDIOP0 ...
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... TPK3 I/O TPK4 I/O TPK5 I/O TPK6 I/O TPK7 I/O TPK8 I/O TPK9 I/O TPK10 I/O TPK11 I/O TPK12 I/O TPK13 I/O TPK14 I/O TPK15 I/O AT91SAM9263 Application Usage Power Supply Function Comments VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 ...
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... PE18 PE19 PE20 PE21 ETXCK PE22 ECRS PE23 ETX0 PE24 ETX1 PE25 ERX0 PE26 ERX1 PE27 ERXER PE28 ETXEN PE29 EMDC PE30 EMDIO PE31 EF100 AT91SAM9263 40 Reset Power Peripheral B State Supply I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 TIOA1 I/O VDDIOP1 ...
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... Using USART2 prevents using EBI0’s NWAIT signal, Chip Select 4 and CompactFlash Chip Enable 2. Using USART1 prevents using EBI0’s Chip Select 5 and CompactFlash Chip Enable1. 10.4.7 NAND Flash Using the NAND Flash interface on EBI1 prevents using Ethernet MAC. 6249I–ATARM–3-Oct-11 AT91SAM9263 41 ...
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... The chip select line may be left active to speed up transfers on the same device 10.5.2 Two-wire Interface • Master Mode only • Compatibility with standard two-wire serial memory • One, two or three bytes for slave address • Sequential read/write operations AT91SAM9263 42 peripherals Sensors and data per chip select 6249I–ATARM–3-Oct-11 ...
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... Time Slot Assigner that can assign time slots to a channel • Channels support mono or stereo up to 20-bit sample length – Variable sampling rate AC97 Codec Interface (48 kHz and below) 6249I–ATARM–3-Oct-11 AT91SAM9263 2 S, TDM Buses, Magnetic Card Reader, etc.) 43 ...
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... Each MCI has two slots, each supporting – One slot for one MultiMediaCard bus ( cards) or – One SD Memory Card • Support for stream, block and multi-block data read and write 10.5.9 CAN Controller • Fully compliant with 16-mailbox CAN 2.0A and 2.0B CAN Controllers AT91SAM9263 44 6249I–ATARM–3-Oct-11 ...
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... Up to 24-bit single scan TFT interfaces supported • gray levels for mono STN and up to 4096 colors for color STN displays • bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN 6249I–ATARM–3-Oct-11 AT91SAM9263 45 ...
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... Vertical and horizontal resolutions up to 2048 x 2048 • Preview Path up to 640*480 • Support for packed data formatting for YCbCr 4:2:2 formats • Preview scaler to generate smaller size image • Programmable frame capture rate AT91SAM9263 46 over this virtual frame buffer 6249I–ATARM–3-Oct-11 ...
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... The ARM926EJ-S provides a complete high performance processor subsystem, including: • an ARM9EJ-S • a Memory Management Unit (MMU) • separate instruction and data AMBA • separate instruction and data TCM interfaces 6249I–ATARM–3-Oct-11 ™ integer core ™ AHB bus interfaces AT91SAM9263 47 ...
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... Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 11.3.2 Switching State The operating state of the ARM9EJ-S core can be switched between: • ARM state and THUMB state using the BX and BLX instructions, and loads to the PC AT91SAM9263 48 ARM926EJ-S Coprocessor Interface Droute ...
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... User mode is the usual ARM program execution state used for executing most application programs • Fast Interrupt (FIQ) mode is used for handling fast interrupts suitable for high-speed data transfer or channel process • Interrupt (IRQ) mode is used for general-purpose interrupt handling 6249I–ATARM–3-Oct-11 AT91SAM9263 49 ...
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... R13 R14 PC CPSR The ARM state register set contains 16 directly-accessible registers r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose AT91SAM9263 50 shows all the registers in all modes. ® ARM9TDMI Modes and Registers Layout Supervisor ...
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... The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operation mode 6249I–ATARM–3-Oct-11 AT91SAM9263 51 ...
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... Reset (highest priority) • Data Abort • FIQ • IRQ • Prefetch Abort • BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) AT91SAM9263 Reserved Jazelle state bit ...
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... ARM Instruction Set Overview The ARM instruction set is divided into: • Branch instructions 6249I–ATARM–3-Oct-11 into LR (current PC(r15 depending on the exception). (current depending on the exception) that causes the program to resume from the correct place on return. AT91SAM9263 53 ...
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... MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC CDP AT91SAM9263 54 gives the ARM instruction mnemonic list. ARM Instruction Mnemonic List Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply ...
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... A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles. Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND AT91SAM9263 Mnemonic Operation Move double from MRRC coprocessor Alternative move of ARM reg MCR2 to coprocessor MCRR Move double to coprocessor ...
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... Caches (ICache, DCache and write buffer) • TCM • MMU • Other system options To control these features, CP15 provides 16 additional registers. See Table 11-5. Register AT91SAM9263 56 Thumb Instruction Mnemonic List (Continued) Operation Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply ...
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... Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. AT91SAM9263 Read/Write Unpredictable/Write Read/write Read/write ...
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... L: Instruction Bit 0 = MCR instruction 1 = MRC instruction • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM, ref. DDI0198B. AT91SAM9263 58 MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2 ...
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... Mapping Details Mapping Size Access Permission By 1M byte Section 64K bytes 4 separated subpages 4K bytes 4 separated subpages 1K byte Tiny Page AT91SAM9263 ® , WindowsCE, and Linux. Subpage Size - 16K bytes 1K byte - 59 ...
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... The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement. AT91SAM9263 60 6249I–ATARM–3-Oct-11 ...
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... DCache can be enabled or disabled by writing either bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM, ref. DDI0222B). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables. 6249I–ATARM–3-Oct-11 AT91SAM9263 61 ...
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... TCM region register (register 9) in CP15 maps TCMs and enables them. The data side of the ARM9EJ-S core is able to access the ITCM. This is necessary to enable code to be loaded into the ITCM, for SWI and emulated instruction handlers, and for accesses to PC-relative literal pools. AT91SAM9263 62 6249I–ATARM–3-Oct-11 ...
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... Any ARM9EJ-S core request that is not words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. Table 11-7 are used for. 6249I–ATARM–3-Oct-11 gives an overview of the supported transfers and different kinds of transactions they AT91SAM9263 63 ...
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... The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. AT91SAM9263 64 Single transfer of word, half word, or byte: • data write (NCNB, NCB, WT that has missed in DCache) • ...
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... AT91SAM9263 Debug and Test 12.1 Overview The AT91SAM9263 features a number of complementary debug and test capabilities. A com- mon JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. An ETM (Embedded Trace Macrocell) provides more sophisticated debug features such as address and data comparators, half-rate clock mode, counters, sequencer and FIFO ...
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... Block Diagram Figure 12-1. Debug and Test Block Diagram TAP: Test Access Port AT91SAM9263 66 ICE/JTAG Boundary TAP Port ARM9EJ-S ICE-RT ETM ARM926EJ-S PDC DBGU TMS TCK TDI NTRST JTAGSEL TDO RTCK POR Reset and TST Test TPK0-TPK15 TPS0-TPS2 TSYNC 2 TCLK DTXD DRXD ...
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... Trace Port Interface Interface ICE/JTAG Trace Connector Connector RS232 AT91SAM9263 Connector AT91SAM9263-based Application shows a test environment example. Test vectors are sent and inter- Test Adaptor JTAG Interface ICE/JTAG Chip n Chip 2 Connector AT91SAM9263 Chip 1 AT91SAM9263-based Application Board In Test AT91SAM9263 Host Debugger Terminal Tester 67 ...
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... Test Mode Select Returned Test Clock JTAG Selection ETM Trace Synchronization Signal Trace Clock Trace ARM Pipeline Status Trace Packet Port Debug Unit Debug Receive Data Debug Transmit Data AT91SAM9263 Type Active Level Input Low Input/Output Low Input High Input Input ...
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... A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM9263 Debug Unit Chip ID value is 0x0196 07A0 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section. 6249I–ATARM–3-Oct-11 ...
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... This allows the maximum frequency of all the trace port signals not to exceed one half of the ARM926EJ-S clock speed. The Embedded Trace Macrocell input and output resources are not used in the AT91SAM9263. The Embedded Trace is a real-time trace module with the capability of tracing the ARM9EJ-S instruction and data ...
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... A data comparator has both a value register and a mask register, therefore it is possible to com- pare only certain bits of a preprogrammed value against the data bus. 6249I–ATARM–3-Oct-11 Trace ARM926EJ-S Control Bus Tracker Trace Enable, View Data TAP Trigger, Sequencer, Counters Controller Scan Chain 6 AT91SAM9263 TPS-TPS0 FIFO TPK15-TPK0 TSYNC ETM9 71 ...
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... Data External Fetch Internal Data Internal Data Half-rate Clocking Mode ARM920T Clock Trace Clock TraceData Half-rate Clocking Mode AT91SAM9263 Start Address End Address 0x0000 0000 0x002F FFFF 0x0000 0000 0x002F FFFF 0x0040 0000 0x004F FFFF 0x0040 0000 0x004F FFFF 0x1000 0000 ...
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... A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 12.5.6.1 JTAG Boundary Scan Register The Boundary Scan Register (BSR) contains 664 bits that correspond to active pins and associ- ated control signals. 6249I–ATARM–3-Oct-11 AT91SAM9263 AT91SAM9263-based Application Board Pin 1Chamfer Figure 12-6 ...
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... Each AT91SAM9263 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 12-3. Bit Number ...
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... AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name PA29 PA30 PA31 EBI1_A0_NBS0 EBI1_A[7:0] EBI1_A1_NWR2 EBI1_A2 EBI1_A3 EBI1_A4 EBI1_A5 EBI1_A6 EBI1_A7 EBI1_A8 EBI1_A[15:8] ...
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... AT91SAM9263 76 AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name EBI1_A22 EBI1_NCS0 EBI1_NCS0/EBI1_NRD/EBI1_NWR_NWR0/ EBI1_NWR_NWR1 EBI1_NRD EBI1_NWR_NWR0 EBI1_NWR_NWR1 EBI1_D0 EBI1_D1 EBI1_D2 EBI1_D3 EBI1_D4 EBI1_D5 EBI1_D6 EBI1_D7 EBI1_D8 ...
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... AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name EBI1_D9 EBI1_D10 EBI1_D11 EBI1_D12 EBI1_D13 EBI1_D14 EBI1_D15 PE20 PE21 PE22 PE23 AT91SAM9263 Associated Pin Type ...
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... AT91SAM9263 78 AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name PE24 PE26 PE25 PE27 EBI1_SDK PE28 PE29 PE30 PE31 RTCK PA0 PA1 Associated Pin Type BSR Cells ...
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... AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 AT91SAM9263 Associated Pin Type ...
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... AT91SAM9263 80 AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name PA13 PA14 PA15 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Associated Pin Type BSR Cells INPUT ...
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... AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 AT91SAM9263 Associated Pin Type ...
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... AT91SAM9263 82 AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 Associated Pin Type BSR Cells INPUT ...
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... AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name PB30 PB31 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 AT91SAM9263 Associated Pin Type ...
Page 84
... AT91SAM9263 84 AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 Associated Pin Type BSR Cells INPUT ...
Page 85
... AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 AT91SAM9263 Associated Pin Type ...
Page 86
... AT91SAM9263 86 AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name PC31 PD0 PD1 PD2 PD3 PD4 N.C. EBI0_A0_NBS0 EBI0_A[7:0] EBI0_A1_NBS2_NWR2 EBI0_A2 EBI0_A3 EBI0_A4 EBI0_A5 EBI0_A6 EBI0_A7 EBI0_A8 ...
Page 87
... AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name EBI0_A11 EBI0_A12 EBI0_A13 EBI0_A14 EBI0_A15 EBI0_A16_BA0 EBI0_A[22:16] EBI0_A17_BA1 EBI0_A18 EBI0_A19 EBI0_A20 EBI0_A21 EBI0_A22 EBI0_NCS0 ...
Page 88
... AT91SAM9263 88 AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name EBI0_D1 EBI0_D2 EBI0_D3 EBI0_D4 EBI0_D5 EBI0_D6 EBI0_D7 EBI0_D8 EBI0_D9 EBI0_D10 EBI0_D11 Associated Pin Type BSR Cells INPUT ...
Page 89
... AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name EBI0_D12 EBI0_D13 EBI0_D14 EBI0_D15 PD5 PD6 PD12 PD7 PD8 PD9 PD10 AT91SAM9263 Associated Pin Type ...
Page 90
... AT91SAM9263 90 AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name PD11 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 Associated Pin Type BSR Cells INPUT IN/OUT ...
Page 91
... AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 PE0 PE1 AT91SAM9263 Associated Pin Type BSR Cells INPUT IN/OUT OUTPUT ...
Page 92
... AT91SAM9263 92 AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 Associated Pin Type BSR Cells INPUT IN/OUT OUTPUT CONTROL INPUT IN/OUT ...
Page 93
... AT91SAM9263 JTAG Boundary Scan Register (Continued) Pin Name PE13 PE14 PE15 PE16 PE17 PE18 PE19 PA16 PA17 PA18 AT91SAM9263 Associated Pin Type BSR Cells INPUT IN/OUT OUTPUT CONTROL ...
Page 94
... MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B0_C03F. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B0C • VERSION[31:28]: Product Version Number Set to 0x0. AT91SAM9263 PART NUMBER 13 12 ...
Page 95
... AT91SAM9263 Boot Program 13.1 Overview The Boot Program integrates different programs permitting download and/or upload into the dif- ferent memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. Then the SD Card Boot program is executed. It looks for a boot.bin file in the root directory of a FAT12/16/32 formatted SD Card ...
Page 96
... Yes Input Frequency Table SD Card Boot No Timeout < NandFlash Boot No Timeout < SPI DataFlash Boot No Timeout < USB Enumeration Run SAM-BA Boot AT91SAM9263 96 No Enable Main Oscillator Yes Download from SD Card (MCI) Yes Download from NandFlash Yes Download from DataFlash (NPCS0) ...
Page 97
... Disable the WatchDog 15. Initialization of the USB Device Port 6249I–ATARM–3-Oct-11 defines the crystals supported by the Boot Program. Crystals Supported by Software Auto-detection (MHz) 3.2768 3.6864 4.608 4.9152 6.144 6.4 7.864320 8.0 12.0 12.288 14.7456 16.0 20 AT91SAM9263 3.84 4.0 5.0 5.24288 6.5536 7.159090 9.8304 10.0 13 13.56 16.367667 17.734470 ...
Page 98
... AT91SAM9263 0x0000_0000 Internal SRAM REMAP 0x0040_0000 Internal ROM “Structure of ARM Vector 6” on page Addressing Mode Offset (24 bits) 99 ...
Page 99
... Code size = 4660 bytes 00001234 B 0x14 eafffffe B 0x18 DataFlash Device Density 1 Mbit 2 Mbits 4 Mbits 8 Mbits 16 Mbits 32 Mbits 64 Mbits AT91SAM9263 Table 13-2 summarizes the Page Size (bytes) Number of Pages 264 512 264 1024 264 2048 264 4096 528 4096 528 8192 1056 ...
Page 100
... LDR or Branch instruction Yes Read the DataFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the and perform the REMAP to jump to the downloaded application End AT91SAM9263 No Jump to next boot solution No 100 ...
Page 101
... Address,# write a word Address, Value# read a word Address,# send a file Address,# receive a file Address, NbOfBytes# go Address# display version No argument AT91SAM9263 “DataFlash Boot” on page 98 for more information Table 13-3. Example O200001,CA# o200001,# H200002,CAFE# h200002,# W200000,CAFEDECA# w200000,# S200000,# R200000,1234# G200200# ...
Page 102
... CRC16 Figure 13-7 6249I–ATARM–3-Oct-11 There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. : Number of bytes in hexadecimal to receive NbOfBytes to 01) shows a transmission using this protocol. AT91SAM9263 102 ...
Page 103
... Windows 98SE to Windows XP. The CDC document, available at Handled Standard Requests Definition Returns the current device configuration value. Sets the device address for all future device access. Sets the device configuration. Returns the current device configuration value. AT91SAM9263 Device 103 ...
Page 104
... Used to clear or disable a specific feature. Handled Class Requests Definition Configures DTE rate, stop bits, parity and number of character bits. Requests current DTE rate, stop bits, parity and number of character bits. RS-232 signal used to tell the DCE device the DTE device is now present. AT91SAM9263 104 ...
Page 105
... Boot ROM does not support high capacity SDCards. contains a list of pins that are driven during the boot program execution. These pins Pins Driven during Boot Program Execution Pin MCCK MCCDA MCDA0 MCDA1 MCDA2 MCDA3 MOSI AT91SAM9263 Size (bytes) 73728 Table 13-1 PIO Line PIOA6 PIOA7 PIOA8 PIOA9 PIOA10 PIOA11 ...
Page 106
... Table 13-7. Peripheral SPI0 SPI0 SPI0 PIOD DBGU DBGU AT91SAM9263 106 Pins Driven during Boot Program Execution (Continued) Pin MISO SPCK NPCS0 NANDCS DRXD DTXD PIO Line PIOA0 PIOA2 PIOA5 PIOD15 PIOC30 PIOC31 6249I–ATARM–3-Oct-11 ...
Page 107
... Block Diagram Figure 14-1. Reset Controller Block Diagram Backup Supply 6249I–ATARM–3-Oct-11 Reset Controller Main Supply POR Startup POR Counter NRST NRST Manager nrst_out WDRPROC wd_fault AT91SAM9263 rstc_irq Reset State Manager proc_nreset user_reset periph_nreset exter_nreset backup_neset SLCK 107 ...
Page 108
... User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN RSTC_MR disables the User Reset trigger. AT91SAM9263 108 Figure 14-2 shows the block diagram of the NRST Manager. ...
Page 109
... The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge. Figure 14-3. BMS Sampling SLCK Core Supply POR output BMS Signal proc_nreset 6249I–ATARM–3-Oct-11 Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs XXX BMS sampling delay = 3 cycles AT91SAM9263 109 ...
Page 110
... SLCK MCK Backup Supply POR output Main Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) AT91SAM9263 110 shows how the General Reset affects the reset signals. Startup Time Processor Startup = 2 cycles XXX EXTERNAL RESET LENGTH BMS Sampling = 2 cycles Any Freq. ...
Page 111
... Main Supply POR. Figure 14-5. Wake-up State SLCK MCK Main Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) 6249I–ATARM–3-Oct-11 Resynch. Processor Startup 2 cycles = 2 cycles XXX EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) AT91SAM9263 Any Freq. 0x1 = WakeUp Reset XXX 111 ...
Page 112
... PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. • PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for AT91SAM9263 112 ...
Page 113
... RSTC_CR has no effect. Figure 14-7. Software Reset SLCK MCK Write RSTC_CR proc_nreset if PROCRST=1 RSTTYP periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 SRCMP in RSTC_SR 6249I–ATARM–3-Oct-11 Any Freq. Resynch. Processor Startup 1 cycle = 2 cycles XXX Any EXTERNAL RESET LENGTH AT91SAM9263 0x3 = Software Reset 8 cycles (ERSTL=2) 113 ...
Page 114
... When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 14-8. Watchdog Reset SLCK MCK wd_fault proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 NRST (nrst_out) AT91SAM9263 114 Any Freq. Processor Startup = 2 cycles Any XXX EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 0x2 = Watchdog Reset 6249I–ATARM–3-Oct-11 ...
Page 115
... If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. 6249I–ATARM–3-Oct-11 proc_nreset signal. AT91SAM9263 Figure 115 ...
Page 116
... Figure 14-9. Reset Controller Status and Interrupt MCK Peripheral Access 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) AT91SAM9263 116 read RSTC_SR 2 cycle resynchronization 6249I–ATARM–3-Oct-11 ...
Page 117
... Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. 6249I–ATARM–3-Oct-11 Name Access RSTC_CR Write-only RSTC_SR Read-only RSTC_MR Read-write AT91SAM9263 Reset Back-up Reset - 0x0000_0001 0x0000_0000 - 0x0000_0000 117 ...
Page 118
... No effect KEY is correct, resets the peripherals. • EXTRST: External Reset effect KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9263 118 KEY 21 ...
Page 119
... Comments Both VDDCORE and VDDBU rising VDDCORE rising Watchdog fault occurred Processor reset required by the software NRST pin detected low AT91SAM9263 – – – – SRCMP NRSTL RSTTYP – ...
Page 120
... This field defines the external reset length. The external reset is asserted during a time of 2 allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9263 120 29 28 ...
Page 121
... RTT_SR RTTINC reset 1 0 32-bit Counter read RTT_SR reset CRTV RTT_SR ALMS set = ALMV AT91SAM9263 RTT_MR RTTINCIEN rtt_int RTT_MR ALMIEN rtt_alarm 32 seconds, corre- 121 ...
Page 122
... RTT RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface AT91SAM9263 122 Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. ...
Page 123
... Real-time Timer (RTT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Alarm Register 0x08 Value Register 0x0C Status Register 6249I–ATARM–3-Oct-11 Name Access RTT_MR Read-write RTT_AR Read-write RTT_VR Read-only RTT_SR Read-only AT91SAM9263 Reset 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000 123 ...
Page 124
... RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. AT91SAM9263 124 – ...
Page 125
... Returns the current value of the Real-time Timer. 6249I–ATARM–3-Oct- ALMV ALMV ALMV ALMV CRTV CRTV CRTV CRTV AT91SAM9263 125 ...
Page 126
... The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR The Real-time Timer has been incremented since the last read of the RTT_SR. AT91SAM9263 126 – ...
Page 127
... Block Diagram Figure 16-1. Periodic Interval Timer 0 MCK 20-bit Counter MCK/16 CPIV Prescaler CPIV 6249I–ATARM–3-Oct-11 PIT_MR PIV = ? 0 1 PIT_PIVR PIT_PIIR AT91SAM9263 set 0 PIT_SR PITS reset 0 1 12-bit Adder read PIT_PIVR PICNT PICNT PIT_MR PITIEN pit_irq 127 ...
Page 128
... PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. AT91SAM9263 128 Figure 16-2 illustrates 6249I– ...
Page 129
... Figure 16-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 6249I–ATARM–3-Oct-11 MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR AT91SAM9263 APB cycle APB cycle restarts MCK Prescaler 129 ...
Page 130
... Periodic Interval Timer (PIT) User Interface Table 16-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register AT91SAM9263 130 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR Read-only PIT_PIIR Read-only Reset 0x000F_FFFF ...
Page 131
... PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt The bit PITS in PIT_SR asserts interrupt. 6249I–ATARM–3-Oct- – – – – – PIV PIV AT91SAM9263 – PITIEN PITEN PIV 131 ...
Page 132
... The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 6249I–ATARM–3-Oct- – – – – – – – – – – – – AT91SAM9263 – – – – – – – – – – – PITS 132 ...
Page 133
... Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 6249I–ATARM–3-Oct- PICNT CPIV CPIV AT91SAM9263 CPIV 133 ...
Page 134
... PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. AT91SAM9263 134 PICNT ...
Page 135
... WDT_MR WDT_CR WDRSTT WDT_MR read WDT_SR or reset 6249I–ATARM–3-Oct-11 WDT_MR WDV reload 1 0 12-bit Down Counter WDD Current Value <= WDD = 0 set WDUNF reset set WDERR reset AT91SAM9263 reload SLCK 1/128 WDT_MR WDRSTEN wdt_fault (to Reset Controller) wdt_int WDFIEN WDT_MR 135 ...
Page 136
... Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. AT91SAM9263 136 6249I–ATARM–3-Oct-11 ...
Page 137
... Figure 17-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 Watchdog Fault AT91SAM9263 137 Watchdog Error WDT_CR = WDRSTT Watchdog Underflow if WDRSTEN WDRSTEN is 0 6249I–ATARM–3-Oct-11 ...
Page 138
... Watchdog Timer (WDT) User Interface Table 17-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register AT91SAM9263 138 Name Access WDT_CR Write-only WDT_MR Read-write Once WDT_SR Read-only Reset - 0x3FFF_2FFF 0x0000_0000 6249I–ATARM–3-Oct-11 ...
Page 139
... WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9263 139 KEY – – – – ...
Page 140
... The Watchdog runs when the processor is in debug state. 1: The Watchdog stops when the processor is in debug state. • WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. AT91SAM9263 140 ...
Page 141
... WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer. AT91SAM9263 141 6249I–ATARM–3-Oct-11 ...
Page 142
... No Watchdog underflow occurred since the last read of WDT_SR least one Watchdog underflow occurred since the last read of WDT_SR. • WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR least one Watchdog error occurred since the last read of WDT_SR. AT91SAM9263 142 – ...
Page 143
... I/O Lines Description Name Description WKUP0 Wake-up 0 input SHDN Shutdown output 6249I–ATARM–3-Oct-11 read SHDW_SR reset WAKEUP0 SHDW_SR set read SYSC_SHSR reset RTTWK SHDW_MR SHDW_CR set AT91SAM9263 SLCK Wake-up SHDN Shutdown Output Controller SHDW_CR Shutdown SHDW Type Input Output 143 ...
Page 144
... SHDW_SR. When using the RTT alarm to wake up the system, the user must ensure that the RTT alarm status flag is cleared before shutting down the system. Otherwise, no rising edge of the status flag may be detected and the wake-up fails. AT91SAM9263 144 6249I–ATARM–3-Oct-11 ...
Page 145
... Shutdown Controller (SHDWC) User Interface Table 18-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register 6249I–ATARM–3-Oct-11 Name Access SHDW_CR Write-only SHDW_MR Read-write SHDW_SR Read-only AT91SAM9263 Reset - 0x0000_0103 0x0000_0000 145 ...
Page 146
... SHDW: Shutdown Command effect KEY is correct, asserts the SHDN pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. AT91SAM9263 146 KEY – – ...
Page 147
... Wake-up Input Transition Selection None. No detection is performed on the wake-up input Low to high level High to low level Both levels change SHDN pin. AT91SAM9263 26 25 – – – – – – – – – ...
Page 148
... At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. • RTTWK: Real-time Timer Wake- wake-up alarm from the RTT occurred since the last read of SHDW_SR least one wake-up alarm from the RTT occurred since the last read of SHDW_SR. AT91SAM9263 148 – ...
Page 149
... The System Controller embeds 20 general-purpose backup registers. 19.2 General Purpose Backup Registers (GPBR) User Interface Table 19-1. Register Mapping Offset Register 0x0 General Purpose Backup Register 0 ... ... 0x4C General Purpose Backup Register 19 6249I–ATARM–3-Oct-11 AT91SAM9263 Name SYS_GPBR0 ... SYS_GPBR 19 Access Reset Read-write – ... ... Read-write – 149 ...
Page 150
... Access Type: Read-write • GPBR_VALUEx: Value of GPBR x 6249I–ATARM–3-Oct- GPBR_VALUEx GPBR_VALUEx GPBR_VALUEx GPBR_VALUEx AT91SAM9263 150 ...
Page 151
... AT91SAM9263 Bus Matrix 20.1 Description Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, which increases the over- all bandwidth. Bus Matrix interconnects 9 AHB Masters to 7 AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency) ...
Page 152
... Eight beat bursts: predicted end of burst is generated at the end of each eight beat boundary inside INCR transfer. 4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside INCR transfer. AT91SAM9263 152 Arbitration”.) Arbitration”.) Section 20.4.1.1 “Undefined Length Section 20.4.1.2 “ ...
Page 153
... This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user. If two or more master’s requests are active at the same time, the master with the highest priority number is serviced first. If two or 6249I–ATARM–3-Oct-11 AT91SAM9263 153 ...
Page 154
... For each slave, the priority of each master may be defined through the Priority Registers for Slaves (MATRIX_PRAS and MATRIX_PRBS). AT91SAM9263 154 6249I–ATARM–3-Oct-11 ...
Page 155
... Priority Register B for Slave 6 0x00C0 - 0x00FC Reserved 0x0100 Master Remap Control Register 0x0104 - 0x010C Reserved 20.5.1 Bus Matrix Master Configuration Registers Register Name:MATRIX_MCFG0...MATRIX_MCFG8 6249I–ATARM–3-Oct-11 AT91SAM9263 Name Access MATRIX_MCFG0 Read-write MATRIX_MCFG1 Read-write MATRIX_MCFG2 Read-write MATRIX_MCFG3 Read-write MATRIX_MCFG4 Read-write ...
Page 156
... The undefined length burst is split into four-beat burst allowing rearbitration at each four-beat burst end. 3: Eight-beat Burst The undefined length burst is split into eight-beat burst allowing rearbitration at each eight-beat burst end. 4: Sixteen-beat Burst The undefined length burst is split into sixteen-beat burst allowing rearbitration at each sixteen-beat burst end. AT91SAM9263 156 – ...
Page 157
... DEFMASTR_TYPE to 0. • ARBT: Arbitration Type 0: Round-Robin Arbitration 1: Fixed Priority Arbitration 2: Reserved 3: Reserved 6249I–ATARM–3-Oct- – – – FIXED_DEFMSTR – – – SLOT_CYCLE AT91SAM9263 – ARBT DEFMSTR_TYPE – – – 157 ...
Page 158
... M8PR: Master 8 Priority Fixed priority of Master 8 for accessing to the selected slave. The higher the number, the higher the priority. AT91SAM9263 158 M7PR – M5PR – M3PR – ...
Page 159
... OHCI USB Host Controller 6249I–ATARM–3-Oct- – – – – – – – – – RCB5 RCB4 RCB3 AT91SAM9263 – – – – – – – – RCB8 RCB2 RCB1 RCB0 159 ...
Page 160
... ITCM_SIZE: Size of ITCM enabled memory block 0000 (No ITCM Memory) 0101 0110 Others: Reserved • DTCM_SIZE: Size of DTCM enabled memory block 0000 (No DTCM Memory) 0101 0110 Others: Reserved AT91SAM9263 160 Name MATRIX_TCMR EBI0_CSA EBI1_CSA – ...
Page 161
... Memories are 1.8V powered Memories are 3.3V powered. 6249I–ATARM–3-Oct- – – – – – – – – – EBI0_CS4A EBI0_CS3A AT91SAM9263 – – – – – VDDIOMSEL – – EBI0_DBPUC – EBI0_CS1A – 161 ...
Page 162
... EBI1_DBPUC: EBI1 Data Bus Pull-Up Configuration 0 = EBI1 D0 - D15 Data Bus bits are internally pulled-up to the VDDIOM1 power supply EBI1 D0 - D15 Data Bus bits are not internally pulled-up. • VDDIOMSEL: Memory voltage selection 0 = Memories are 1.8V powered Memories are 3.3V powered. AT91SAM9263 162 – ...
Page 163
... Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus bits three chip select lines (NCS[2:0]) and several control pins that are generally multiplexed between the different external Memory Controllers. 6249I–ATARM–3-Oct-11 AT91SAM9263 163 ...
Page 164
... Block Diagram 21.2.1 External Bus Interface 0 Figure 21-1 Figure 21-1. Organization of the External Bus Interface 0 Bus Matrix AHB Address Decoders AT91SAM9263 164 shows the organization of the External Bus Interface 0. External Bus Interface 0 SDRAM Controller MUX Static Logic Memory Controller CompactFlash Logic NAND Flash Logic ...
Page 165
... External Bus Interface 1. External Bus Interface 1 SDRAM Controller Static Memory Controller NAND Flash Logic ECC Controller Chip Select Assignor User Interface APB AT91SAM9263 D[15:0] A0/NBS0 MUX Logic A1/NWR2/NBS2 A[15:2], A[20:18] A16/BA0 A17/BA1 NCS0 NRD NWR0/NWE NWR1/NBS1 A21/NANDALE A22/NANDCLE SDWE ...
Page 166
... EBI0_NWR0 - EBI0_NWR3 Write Signals EBI0_NBS0 - EBI0_NBS3 Byte Mask Signals EBI0_SDA10 SDRAM Address 10 Line 6249I–ATARM–3-Oct-11 EBI SMC EBI for CompactFlash Support EBI for NAND Flash Support SDRAM Controller AT91SAM9263 Type Active Level I/O Output Input Low Output Low Output Low Output ...
Page 167
... Controller in use at the moment. Table 21-3 on page 168 EBI pins. 6249I–ATARM–3-Oct-11 EBI SMC EBI for NAND Flash Support SDRAM Controller details the connections between the two Memory Controllers and the AT91SAM9263 Type Active Level I/O Output Input Low Output Low ...
Page 168
... EBIx_A[14:13] EBIx_A[22:15] EBIx_A[25:23] EBIx_D[31:0] Notes: 6249I–ATARM–3-Oct-11 EBIx Pins and Memory Controllers I/O Lines Connections (1) EBIx Pins ( indicates Only for EBI0 AT91SAM9263 SDRAMC I/O Lines NBS1 NWR1/NUB Not Supported SMC_A0/NLB Not Supported SMC_A1 SDRAMC_A[9:0] SMC_A[11:2] SDRAMC_A10 Not Supported ...
Page 169
... A[22:24 ( (1) WE NUB – – AT91SAM9263 4 x 8-bit 2 x 16-bit 32-bit Static Static Static Devices Devices D15 D16 - D23 D16 - D23 D24 - D31 D24 - D31 (3) – NLB (2) (4) WE NLB A[0:20] A[0:20] ...
Page 170
... CFCS0 (1) – CFCS1 – – – – – OE – WE DQM1 IOR DQM3 IOW – CE1 – CE2 AT91SAM9263 CompactFlash True IDE Mode NAND Flash (EBI0 only) SMC I/O0-I/O7 ( I/O8-I/O15 – – A0 – A1 – A[2:10] – – – – – ...
Page 171
... CLK – CKE – RAS – CAS – WE – – WAIT – CD1 or CD2 – – – – AT91SAM9263 CompactFlash True IDE Mode NAND Flash (EBI0 only) SMC – – – – – – – – – – WAIT – CD1 or CD2 – ...
Page 172
... A10 A16/BA0 RAS BA0 A17/BA1 CAS BA1 DQM NBS2 128K x 8 SRAM A1-A17 D0-D7 A0-A16 D0-D7 D8-D15 CS OE NRD/NOE NRD/NOE WE A0/NWR0/NBS0 NWR1/NBS1 AT91SAM9263 SDRAM D8-D15 D0-D7 CS CLK A0-A9, A11 A2-A11, A13 CKE SDWE A10 SDA10 WE BA0 A16/BA0 RAS BA1 A17/BA1 CAS DQM NBS1 ...
Page 173
... Static Memory Controller For information on the Static Memory Controller, refer to the Static Memory Controller section. 21.5.4 SDRAM Controller For information on the SDRAM Controller, refer to the SDRAM section. 21.5.5 ECC Controller For information on the ECC Controller, refer to the ECC section. 6249I–ATARM–3-Oct-11 AT91SAM9263 173 ...
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... Offset 0x0080 0000 Offset 0x0040 0000 Offset 0x0000 0000 The A22 pin is used to drive the REG signal of the CompactFlash Device (except in True IDE mode). AT91SAM9263 Figure True IDE Alternate Mode Space True IDE Mode Space I/O Mode Space Common Memory Mode Space ...
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... Access to Odd Byte on D[15:8] Don’t 1 Access to Even Byte on D[7:0] Care 1 8 bits Access to Odd Byte on D[7:0] 1 – AT91SAM9263 Mode Base Address Attribute Memory Common Memory I/O Mode True IDE Mode Alternate True IDE Mode to enable the required access type. SMC Access Mode Byte Select ...
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... Common Memory I/O Mode True IDE Mode 6249I–ATARM–3-Oct-11 demonstrates a schematic representation of this logic. External Bus Interface SMC A23 A22 NRD_NOE NWR0_NWE CFOE CFWE NRD NWR0_NWE AT91SAM9263 CompactFlash Logic CFOE 1 1 CFWE 1 0 CFIOR 1 CFIOW 1 1 CFIOR ...
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... CompactFlash Signals CS5A = 1 CFCS1 Access to CompactFlash Device CompactFlash Signals CFOE CFWE CFIOR CFIOW CFRNW AT91SAM9263 illustrate the multiplexing of the Compact- Table 21-9 remain shared between all memory areas when the EBI Signals CS4A = 0 CS5A = 0 NCS4 NCS5 Access to Other EBI Devices EBI Signals ...
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... Figure 21-6. CompactFlash Application Example 6249I–ATARM–3-Oct-11 illustrates an example of a CompactFlash application. CFCS0 and EBI D[15:0] A25/CFRNW NCS4/CFCS0 CD (PIO) A[10:0] A22/REG NOE/CFOE NWE/CFWE NWR1/CFIOR NWR3/CFIOW CFCE1 CFCE2 NWAIT AT91SAM9263 CompactFlash Connector D[15:0] DIR /OE _CD1 _CD2 /OE A[10:0] _REG _OE _WE _IORD _IOWR _CE1 _CE2 _WAIT ...
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... For details on these waveforms, refer to the Static Memory Controller section. 6249I–ATARM–3-Oct-11 SMC NCSx NRD NWR0_NWE AT91SAM9263 for more information. For details on these wave- NAND Flash Logic NANDOE NANDWE Figure 21-7 on page “NAND Flash NANDOE NANDWE ...
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... NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCSx is not selected, preventing the device from returning to standby mode. Figure 21-8. NAND Flash Application Example Note: AT91SAM9263 180 D[7:0] A[22:21] NCSx/NANDCS ...
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... D[0..15] A[0..14] (Not used A12 A10 A11 SDA10 A13 BA0 BA1 A14 SDCKE SDCK A0 CFIOR_NBS1_NWR1 CAS RAS SDWE SDCS_NCS1 AT91SAM9263 DQ0 MT48LC16M16A2 MT48LC16M16A2 DQ1 DQ2 DQ3 D4 29 ...
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... EBI1 SDCS, SDWE, SDCKE, SDA10, RAS and CAS signals are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. The SDRAM initialization sequence is described in the section “SDRAM Device Initialization” in “SDRAM Controller (SDRAMC)”. AT91SAM9263 182 U1 U1 ...
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... Flash timings, the data bus width and the system bus frequency. 6249I–ATARM–3-Oct- 10K 10K 3V3 R2 R2 10K 10K AT91SAM9263 K9F2G08U0M K9F2G08U0M D0 29 CLE I/ ALE R ...
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... Hardware Configuration D[0..15] CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 21.6.4.2 Software Configuration The software configuration is the same as for an 8-bit NAND Flash except the data bus width programmed in the mode register of the Static Memory Controller. AT91SAM9263 184 CLE 17 ALE ...
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... A17 A19 16 AT49BV6416 AT49BV6416 A18 A20 15 A19 A21 10 A20 A22 9 A21 VCCQ 12 RESET 3V3 VPP TSOP48 PACKAGE AT91SAM9263 D0 29 DQ0 D1 31 DQ1 D2 33 DQ2 D3 35 DQ3 D4 38 DQ4 D5 40 DQ5 D6 42 DQ6 D7 44 DQ7 D8 30 DQ8 D9 32 ...
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... A10 3V3 A22/REG CFWE CFOE CFIOW CFIOR CFCE2 CFCE1 CFRST (ANY PIO) CFIRQ (ANY PIO) NWAIT AT91SAM9263 186 MN1A MN1A CF_D15 A2 A5 1B1 1A1 CF_D14 A1 A6 1B2 1A2 CF_D13 B2 B5 1B3 1A3 CF_D12 B1 B6 1B4 1A4 CF_D11 ...
Page 187
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. 6249I–ATARM–3-Oct-11 AT91SAM9263 187 ...
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... A10 3V3 A22/REG CFWE CFOE CFIOW CFIOR CFCE2 CFCE1 CFRST (ANY PIO) CFIRQ (ANY PIO) NWAIT AT91SAM9263 188 MN1A MN1A CF_D15 A2 A5 1B1 1A1 CF_D14 A1 A6 1B2 1A2 CF_D13 B2 B5 1B3 1A3 CF_D12 B1 B6 1B4 1A4 CF_D11 ...
Page 189
... Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 and/or SMC_CS5 (for Slot Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. 6249I–ATARM–3-Oct-11 AT91SAM9263 189 ...
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... AT91SAM9263 190 6249I–ATARM–3-Oct-11 ...
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... Description SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select Signals Row Signal Column Signal SDRAM Write Enable Data Mask Enable Signals Address Bus Data Bus AT91SAM9263 Type Active Level Output Output High Output Low Output Output Low Output ...
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... SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0] Row[12:0] Notes: 1. M[1:0] is the byte address inside a 32-bit word. 3. Bk[1] = BA1, Bk[0] = BA0. AT91SAM9263 234 Table 23-2 to Table 23-7 illustrate the SDRAM device memory mapping seen by the CPU Address Line Row[10:0] Row[10:0] ...
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... Row[11:0] Row[11:0] Row[11:0] Row[11:0] CPU Address Line Row[12:0] Row[12:0] Row[12:0] Row[12:0] A NOP command is issued to the SDRAM devices. The application must set Mode to AT91SAM9263 Column[7:0] Column[8:0] Column[9:0] Column[10: Column[7:0] ...
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... After initialization, the SDRAM devices are fully functional. Note: 6249I–ATARM–3-Oct- strongly recommended to respect the instructions stated in cess in order to be certain that the subsequent commands issued by the SDRAMC will be taken into account. AT91SAM9263 Step 5 of the initialization pro- 236 ...
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... This interrupt may be ORed with other System Peripheral interrupt lines and is finally provided as the System Interrupt Source (Source 1) to the AIC (Advanced Interrupt Controller). Using the SDRAM Controller interrupt requires the AIC to be programmed first. 6249I–ATARM–3-Oct- 1st Auto-refresh 8th Auto-refresh AT91SAM9263 MRD MRS Command Valid Command 237 ...
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... For definition of these timing parameters, refer to the RCD 249. This is described col a col b col c col d Dna Dnb Dnc Dnd AT91SAM9263 Figure 23-2 below. col e col f col g col h col i col j Dne Dnf Dng Dnh Dni Dnj ) ...
Page 197
... Figure 23-3. Read Burst, 32-bit SDRAM Access SDCS SDCK SDRAMC_A[12:0] RAS CAS SDWE D[31:0] (Input) 6249I–ATARM–3-Oct- CAS = 2 RCD Row n col a col b col c Dna AT91SAM9263 col d col e col f Dnb Dnc Dnd Dne Dnf 239 ...
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... RAS CAS SDWE D[31:0] Dna Dnb 6249I–ATARM–3-Oct-11 Figure 23-4 below col d Row m Dnc Dnd AT91SAM9263 ) command and the active/read ( CAS = 2 RCD col a col b col c col d Dma Dmb Dmc ) com- RCD col e Dmd Dme 240 ...
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... See Figure 23-5. Refresh Cycle Followed by a Read Access SDCS SDCK Row n col c col d SDRAMC_A[12:0] RAS CAS SDWE D[31:0] Dnb Dnc Dnd (input) 6249I–ATARM–3-Oct- AT91SAM9263 Figure 23- CAS = 2 RCD col a Row m Dma 241 ...
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... Drive Strength (DS) parameters must be set in the Low Power Register and transmitted to the low-power SDRAM during initialization. The SDRAM device must remain in self-refresh mode for a minimum period of t remain in self-refresh mode for an indefinite period. This is described in 6249I–ATARM–3-Oct-11 AT91SAM9263 and may RAS Figure 23-6. ...