SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 123

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI0198D
IRADDR
IRWAIT
IRSEQ
IRCS
IRRD
CLK
In cycle T1, a nonsequential request is made to address A and IRWAIT is asserted.
In cycle T2, IRSEQ is asserted because of the wait-state. IRWAIT is deasserted. IRCS
is unknown.
In cycle T3, the access to A completes and a sequential request is made to A+1. IRSEQ
is HIGH and IRWAIT is LOW
In cycle T4, the access to A+1 completes. No new request is issued. The values of
IRSEQ and IRWAIT are unknown.
In cycle T5, a nonsequential request is made to address B and IRWAIT is asserted
In cycle T6, IRSEQ is asserted because of the wait-state. IRWAIT is deasserted, IRCS
is unknown.
In cycle T7, the access to B completes.
For systems that also require DMA access to non zero wait state memories, the WAIT
signal is used to stall the ARM92EJ-S processor for both wait states and DMA
arbitration. Apart from the DRWD/IRWD write data signals, the information required
to perform an access is only valid during the request cycle for that access. If a TCM
access is postponed because of DMA, this information must be captured at the end of
the request cycle.
Figure 5-10 on page 5-16 shows an example of a system where DMA access is required
to a memory that has a single wait state for nonsequential accesses.
Copyright © 2001-2003 ARM Limited. All rights reserved.
T1
A
T2
T3
A+1
I(A)
Figure 5-9 Cycle timing of loopback circuit
T4
I(A+1)
T5
Tightly-Coupled Memory Interface
B
T6
T7
I(B)
5-15