SAM9263 Atmel Corporation, SAM9263 Datasheet - Page 3

• Manufacturer Part Number: SAM9263
• Manufacturer: Atmel Corporation

Specifications of SAM9263

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Can: 1
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 96
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Contents
ARM926EJ-S Technical Reference Manual
ARM DDI0198D
Chapter 1
Chapter 2
Chapter 3
Preface
Introduction
1.1
Programmer’s Model
2.1
2.2
2.3
Memory Management Unit
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Copyright © 2001-2003 ARM Limited. All rights reserved.
About this manual ........................................................................................ xvi
Feedback ..................................................................................................... xxi
About the ARM926EJ-S processor ............................................................. 1-2
About the programmer’s model ................................................................... 2-2
Summary of ARM926EJ-S system control coprocessor (CP15) registers .. 2-3
Register descriptions .................................................................................. 2-7
About the MMU ........................................................................................... 3-2
Address translation ..................................................................................... 3-5
MMU faults and CPU aborts ..................................................................... 3-21
Domain access control .............................................................................. 3-24
Fault checking sequence .......................................................................... 3-26
External aborts .......................................................................................... 3-29
TLB structure ............................................................................................ 3-31
iii