SAM9G20 Atmel Corporation, SAM9G20 Datasheet - Page 158
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SAM9G20
Manufacturer Part Number
SAM9G20
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G20.pdf
(42 pages)
5.SAM9G20.pdf
(832 pages)
Specifications of SAM9G20
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
7
Ssc
1
Ethernet
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
95
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G20 PDF datasheet #4
- SAM9G20 PDF datasheet #5
- Current page: 158 of 248
- Download datasheet (2Mb)
Coprocessor Interface
8.1
8.1.1
8-2
About the ARM926EJ-S external coprocessor interface
Overview
The ARM926EJ-S supports the connection of on-chip coprocessors to the ARM9EJ-S
core through an external coprocessor interface. All types of coprocessor instructions are
supported.
Coprocessors determine the instructions that they have to execute by using a pipeline
follower in the coprocessor. As each instruction arrives from memory it enters both the
ARM9EJ-S pipeline and the coprocessor pipeline. To avoid a critical path for the
instruction being latched by the coprocessor, the coprocessor pipeline must operate one
clock cycle behind the ARM9EJ-S core pipeline.
The two pipelines are synchronized by stalling the ARM9EJ-S core pipeline in its first
Execute cycle whenever an external coprocessor instruction moves from the Decode to
the Execute stage.
To enable coprocessors to continue execution of coprocessor data operations while the
ARM9EJ-S core pipeline is stalled (for example, while waiting for a cache linefill to
occur), the coprocessor receives the clock CLK, and a clock enable signal CPCLKEN.
You can use these to produce a gated coprocessor clock with the circuit shown in
Figure 8-1.
Figure 8-2 indicates the timing for these signals and when the coprocessor pipeline
must advance its state.
Copyright © 2001-2003 ARM Limited. All rights reserved.
CLK
CPCLKEN
Coproc clock
Figure 8-1 Producing a coprocessor clock
CPCLKEN
Figure 8-2 Coprocessor clocking
CLK
ARM DDI0198D
Coproc clock
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