SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 158
SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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20.1.4
Table 20-1.
20.1.5
20.1.6
158
Name
DDR_D0 - DDR_D15
DDR_A0 - DDR_A13
DDR_DQM0 - DDR_DQM1
DDR_DQS0 - DDR_DQS1
DDR_VREF
DDR_CS
DDR_CLK - DDR_CLK#
DDR_CKE
DDR_RAS
DDR_CAS
DDR_WE
DDR_BA0 - DDR_BA1
SAM9M10
I/O Lines Description
Product Dependencies
Implementation Example
DDR2 I/O Lines Description
The pins used for interfacing the DDR2 memory are not multiplexed with the PIO lines.
The following hardware configuration is given for illustration only. The user should refer to the
memory manufacturer web site to check current device availability.
Function
Data Mask
Data Strobe
Reference Voltage for DDR2 operations, typically 0.9V
Chip Select
DDR2 Differential Clock
Clock enable
Row signal
Column signal
Write enable
Bank Select
Data Bus
Address Bus
DDR2/LPDDR Controller
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Type
Input
I/O
6355D–ATARM–7-Sep-11
Active Level
High
Low
Low
Low
Low
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