SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 708
SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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SAM9M10
WRITE_SINGLE_BLOCK Operation using DMA Controller
1. Wait until the current command execution has successfully terminated.
2. Program the block length in the card. This value defines the value block_length.
3. Program the block length in the HSMCI configuration register with block_length value.
4. Program HSMCI_DMA register with the following fields:
5. Issue a WRITE_SINGLE_BLOCK command writing HSMCI_ARG then HSMCI_CMDR.
6. Program the DMA Controller.
a. Check that CMDRDY and NOTBUSY fields are asserted in HSMCI_SR
– OFFSET field with dma_offset.
– CHKSIZE is user defined and set according to DMAC_DCSIZE.
– DMAEN is set to true to enable DMA hardware handshaking in the HSMCI. This bit
a. Read the channel Register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMAC transfer by
c. Program the channel registers.
d. The DMAC_SADDRx register for channel x must be set to the location of the
e. The DMAC_DADDRx register for channel x must be set with the starting address of
f.
g. Program DMAC_CTRLBx register for channel x with the following field’s values:
h. Program DMAC_CFGx register for channel x with the following field’s values:
was previously set to false.
reading the DMAC_EBCISR register.
source data. When the first data location is not word aligned, the two LSB bits
define the temporary value called dma_offset. The two LSB bits of
DMAC_SADDRx must be set to 0.
the HSMCI_FIFO address.
Program DMAC_CTRLAx register of channel x with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–DCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with CEILING((block_length + dma_offset) / 4), where
–DST_INCR is set to INCR, the block_length value must not be larger than the
–SRC_INCR is set to INCR.
–FC field is programmed with memory to peripheral flow control mode.
–both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
–FIFOCFG defines the watermark of the DMAC channel FIFO.
–DST_H2SEL is set to true to enable hardware handshaking on the destination.
–DST_PER is programmed with the hardware handshaking ID of the targeted
the ceiling function is the function that returns the smallest integer not less than
x.
HSMCI_FIFO aperture.
DMA controller is able to prefetch data and write HSMCI simultaneously.
HSMCI Host Controller.
6355D–ATARM–7-Sep-11
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