SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 120
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SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 120 of 248
- Download datasheet (2Mb)
Tightly-Coupled Memory Interface
5-12
In cycle T1, the ARM926EJ-S internal TCM controller is idle and DRIDLE is asserted.
DRDMAEN is asserted, and consequently the value of DRDMAADDR is propagated
onto DRADDR, and DRCS is asserted (DRDMACS = 1). DRSEQ is forced LOW.
In cycle T2, the ARM926EJ-S internal TCM controller is no longer idle, and DRIDLE
is deasserted. A nonsequential request is made to address B.
In cycle T3, a sequential request is made to address B+1 and DRSEQ is asserted
In cycle T4, the ARM926EJS internal TCM controller attempts to output values
corresponding to a sequential request to address B+2. DRDMAEN is asserted, and the
value of DRADDR and DRSEQ change accordingly. The ARM926EJ-S TCM
controller is stalled.
In cycle T5, DRDMAEN is deasserted and the ARM926EJ-S TCM controller re-issues
the request to address B+2. Because of the intervening DMA access, DRSEQ is
deasserted for the repeated request.
In cycle T6, a sequential request is made to address B+3 and DRSEQ is re-asserted.
DMA accesses can be made to the ITCM using the IRDMAEN, IRDMACS, and
IRDMAADDR signals but, unlike the DTCM, simultaneous access by the
ARM926EJ-S and DMA is not supported. This means that ITCM DMA must not take
place while executing code from the ITCM.
DRDMAADDR
DRDMAEN
DRDMACS
Copyright © 2001-2003 ARM Limited. All rights reserved.
DRADDR
DRIDLE
DRSEQ
DRCS
CLK
Figure 5-5 DMA access interaction with normal DTCM accesses
T1
A
A
T2
B
T3
B+1
B+2
T4
C
C
T5
B+2
ARM DDI0198D
T6
B+3
B+3
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