SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 160
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 160 of 248
- Download datasheet (2Mb)
Coprocessor Interface
8.2
8-4
CPLATECANCEL
CPDOUT[31:0]
CPINSTR[31:0]
CPDIN[31:0]
CHSDE[1:0]
CHSEX[1:0]
Coprocessor
nCPMREQ
CPPASS
pipeline
LDC/STC
LDC
STC
CLK
Fetch
LDC
The cycle timing for this operation is shown in Figure 8-3.
In Figure 8-3 four words of data are transferred. The number of words transferred is
determined by how the coprocessor drives the CHSDE[1:0] and CHSEX[1:0] buses.
As with all other instructions, the ARM9EJ-S core performs the main decode off the
rising edge of the clock during the Decode stage. From this, the core commits to
executing the instruction and so performs an instruction fetch. The coprocessor
instruction pipeline keeps in step with the ARM9EJ-S core by monitoring nCPMREQ.
nCPMREQ is an active LOW signal that indicates if the ARM9EJ-S pipeline has
advanced. CPINSTR is updated with the fetched instruction in the next cycle. This
means that the instruction currently on CPINSTR must enter the Decode stage of the
coprocessor pipeline, and that the instruction in the Decode stage of the coprocessor
pipeline must enter its Execute stage.
During the Execute stage, the condition codes are combined with the flags to determine
if the instruction executes or not. The output CPPASS is asserted HIGH if the
instruction in the Execute stage of the coprocessor pipeline:
•
•
Copyright © 2001-2003 ARM Limited. All rights reserved.
Decode
is a coprocessor instruction
has passed its condition codes.
GO
Execute
(GO)
GO
Execute
(GO)
GO
Execute
(GO)
LAST
Execute
(LAST)
Figure 8-3 LDC/STC cycle timing
Ignored
Memory
ARM DDI0198D
Write
Related parts for SAM9RL64
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Low-Voltage Voice-Switched IC for Hands-Free Operation
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
MONOLITHIC INTEGRATED FEATUREPHONE CIRCUIT
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
AM-FM Receiver IC U4255BM-M
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Monolithic Integrated Feature Phone Circuit
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Multistandard Video-IF and Quasi Parallel Sound Processing
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
High-performance EE PLD
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
8-bit Flash Microcontroller
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
2-Wire Serial EEPROM
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
U6046BREAR WINDOW HEATING TIMER / LONG-TERM TIMER
Manufacturer:
ATMEL Corporation
Datasheet: