SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 73
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 73 of 248
- Download datasheet (2Mb)
ARM DDI0198D
31
Coarse page table base address
Section base address
Fine page table base address
A section descriptor provides the base address of a 1MB block of memory.
The page table descriptors provide the base address of a page table that contains
second-level descriptors. There are two sizes of page table:
•
•
First-level descriptor bit assignments are shown in Table 3-2.
Bits
Section
[31:20]
[19:12]
[11:10]
[9]
[8:5]
[4]
Copyright © 2001-2003 ARM Limited. All rights reserved.
coarse page tables have 256 entries, splitting the 1MB that the table describes into
4KB blocks
fine page tables have 1024 entries, splitting the 1MB that the table describes into
1KB blocks.
Coarse
[31:10]
-
-
[9]
[8:5]
[4]
20 19
Fine
[31:12]
-
-
[11:9]
[8:5]
[4]
Description
These bits form the corresponding bits of the physical
address.
Should Be Zero.
Access permission bits. Access permissions and domains on
page 3-3 and Fault address and fault status registers on
page 3-21 show how to interpret the access permission bits.
Should Be Zero.
Domain control bits.
Must be 1.
12 11 10 9 8
AP
Domain
Domain
Domain
Table 3-2 First-level descriptor bits
Figure 3-4 First-level descriptor
5 4 3 2 1 0
1
1 C B 1 0
1
0 0
0 1
1 1
Memory Management Unit
Fault
Coarse page table
Section
Fine page table
3-9
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