ATmega325PA Atmel Corporation, ATmega325PA Datasheet - Page 139
ATmega325PA
Manufacturer Part Number
ATmega325PA
Description
Manufacturer
Atmel Corporation
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17.4
17.4.1
8285D–AVR–06/11
Register Description
GTCCR – General Timer/Counter Control Register
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding pres-
caler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and
can be configured to the same value without the risk of one of them advancing during configura-
tion. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware,
and the Timer/Counters start counting simultaneously.
• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor-
mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1
and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both
timers.
Bit
0x23 (0x43)
Read/Write
Initial Value
TSM
R/W
7
0
R
6
–
0
R
5
–
0
R
4
–
0
R
3
–
0
R
2
–
0
PSR2
R/W
1
0
PSR10
R/W
0
0
GTCCR
139
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