ATmega325PA Atmel Corporation, ATmega325PA Datasheet - Page 147
ATmega325PA
Manufacturer Part Number
ATmega325PA
Description
Manufacturer
Atmel Corporation
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18.7.4
8285D–AVR–06/11
Phase Correct PWM Mode
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare
matches between OCR2A and TCNT2.
Figure 18-6. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the inter-
rupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin.
Setting the COM2A[1:0] bits to two will produce a non-inverted PWM and an inverted PWM out-
put can be generated by setting the COM2A[1:0] to three (See
actual OC2A value will only be visible on the port pin if the data direction for the port pin is set as
output. The PWM waveform is generated by setting (or clearing) the OC2A Register at the com-
pare match between OCR2A and TCNT2, and clearing (or setting) the OC2A Register at the
timer clock cycle the counter is cleared (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result
in a constantly high or low output (depending on the polarity of the output set by the COM2A[1:0]
bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-
ting OC2A to toggle its logical level on each compare match (COM2A[1:0[ = 1). The waveform
generated will have a maximum frequency of f
ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output
Compare unit is enabled in the fast PWM mode.
The phase correct PWM mode (WGM2[1:0] = 1) provides a high resolution phase correct PWM
waveform generation option. The phase correct PWM mode is based on a dual-slope operation.
TCNTn
OCnx
OCnx
Period
1
2
3
f
OCnxPWM
4
oc2
5
=
= f
----------------- -
N 256
f
clk_I/O
clk_I/O
⋅
6
/2 when OCR2A is set to zero. This fea-
7
Table 18-4 on page
OCRnx Interrupt Flag Set
OCRnx Update and
TOVn Interrupt Flag Set
(COMnx1:0 = 2)
(COMnx1:0 = 3)
155). The
147
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