ATmega325PA Atmel Corporation, ATmega325PA Datasheet - Page 299

• Manufacturer Part Number: ATmega325PA
• Manufacturer: Atmel Corporation

27.8.2
8285D–AVR–06/11
Serial Programming Algorithm
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
Figure 27-10. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P, data is clocked on
the rising edge of SCK.
When reading data from the
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P, data is clocked on
the falling edge of SCK. See
To program and verify the
ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P in the serial pro-
gramming mode, the following sequence is recommended (See four byte instruction formats in
Table
1. Power-up sequence:
2. Wait for at least 20ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of synchro-
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin MOSI.
nization. When in sync. the second byte (0x53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all four
27-16):
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
2. V
XTAL1 pin.
CC
- 0.3V < AVCC < V
CC
Figure 27-11
and GND while RESET and SCK are set to “0”. In some sys-
MOSI
MISO
SCK
ck
ck
CC
< 12MHz, 3 CPU clock cycles for f
< 12MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 1.8 - 5.5V
XTAL1
RESET
GND
for timing details.
(1)
AVCC
VCC
+1.8 - 5.5V
+1.8 - 5.5V
(2)
ck
ck
≥ 12MHz
≥ 12MHz
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