ATmega325PA Atmel Corporation, ATmega325PA Datasheet - Page 141

• Manufacturer Part Number: ATmega325PA
• Manufacturer: Atmel Corporation

18.2.2
18.3
18.4
8285D–AVR–06/11
Timer/Counter Clock Sources
Counter Unit
Definitions
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from
the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by
the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock
source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac-
tive when no clock source is selected. The output from the Clock Select logic is referred to as the
timer clock (clk
The double buffered Output Compare Register (OCR2A) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the Waveform Generator to gener-
ate a PWM or variable frequency output on the Output Compare pin (OC2A).
Compare Unit” on page 142.
Flag (OCF2A) which can be used to generate an Output Compare interrupt request.
Many register and bit references in this document are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 2. However, when using the register or bit
defines in a program, the precise form must be used, i.e., TCNT2 for accessing Timer/Counter2
counter value and so on.
The definitions in
Table 18-1.
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clk
bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter
Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see
– Asynchronous Status Register” on page
”Timer/Counter Prescaler” on page
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
18-2
Figure 18-2. Counter Unit Block Diagram
BOTTOM
MAX
TOP
shows a block diagram of the counter and its surrounding environment.
DATA BUS
Timer/Counter Definitions
T2
The counter reaches the BOTTOM when it becomes zero (0x00).
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR2A Register. The assignment is dependent
on the mode of operation.
TCNTn
).
Table 18-1
are also used extensively throughout the section.
for details. The compare match event will also set the Compare
direction
T2
count
clear
153.
bottom
is by default equal to the MCU clock, clk
Control Logic
157. For details on clock sources and prescaler, see
top
TOVn
(Int.Req.)
clk
Tn
Prescaler
Oscillator
T/C
I/O
. When the AS2
clk
I/O
See ”Output
TOSC2
TOSC1
”ASSR
Figure
141