SAM3N0B Atmel Corporation, SAM3N0B Datasheet - Page 506

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SAM3N0B

Manufacturer Part Number
SAM3N0B
Description
Manufacturer
Atmel Corporation
Datasheets
29.3
Figure 29-1. UART Functional Block Diagram
Table 29-1.
29.4
29.4.1
29.4.2
506
506
Pin Name
URXD
UTXD
Block Diagram
Product Dependencies
Management
SAM3N
SAM3N
Controller
I/O Lines
Power Management
Power
UART Pin Description
APB
Peripheral
Bridge
The UART pins are multiplexed with PIO lines. The programmer must first configure the corre-
sponding PIO Controller to enable I/O line operations of the UART.
Table 29-2.
The UART clock is controllable through the Power Management Controller. In this case, the pro-
grammer must first configure the PMC to enable the UART clock. Usually, the peripheral
identifier used for this purpose is 1.
Description
UART Receive Data
UART Transmit Data
Instance
UART0
UART0
UART1
UART1
MCK
I/O Lines
Baud Rate
Generator
UART
Peripheral DMA Controller
URXD0
URXD1
UTXD0
UTXD1
Signal
Transmit
Interrupt
Receive
Control
Type
Input
Output
I/O Line
uart_irq
PA10
PB2
PB3
PA9
Parallel
Output
Input/
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
Peripheral
URXD
UTXD
A
A
A
A

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