AD7193 Analog Devices, AD7193 Datasheet - Page 24
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AD7193
Manufacturer Part Number
AD7193
Description
4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA
Manufacturer
Analog Devices
Datasheet
1.AD7193.pdf
(56 pages)
Specifications of AD7193
Resolution (bits)
24bit
# Chan
4
Sample Rate
n/a
Interface
Ser,SPI
Analog Input Type
Diff-Uni,SE-Uni,Usr-Defined Range/Offset
Ain Range
± (Vref/Gain)
Adc Architecture
Sigma-Delta
Pkg Type
SOP
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AD7193
MODE REGISTER
RS2, RS1, RS0 = 001; Power-On/Reset = 0x080060
The mode register is a 24-bit register from which data can be
read or to which data can be written. This register is used to
select the operating mode, the output data rate, and the clock
source. Table 20 outlines the bit designations for the mode
MR23
MD2(0)
MR15
SINC3(0)
MR7
FS7(0)
Table 20. Mode Register (MR) Bit Designations
Bit Location
MR23 to MR21
MR20
MR19, MR18
MR17, MR16
MR15
MR14
MR13
MR22
MD1(0)
MR14
0
MR6
FS6(1)
Bit Name
MD2 to MD0
DAT_STA
CLK1, CLK0
AVG1, AVG0
SINC3
0
ENPAR
MR21
MD0(0)
MR13
ENPAR(0)
MR5
FS5(1)
Description
Mode select bits. These bits select the operating mode of the AD7193 (see Table 21).
This bit enables the transmission of status register contents after each data register read. When DAT_STA
is set, the contents of the status register are transmitted along with each data register read. This function
is useful when several channels are selected because the status register identifies the channel to which
the data register value corresponds.
These bits select the clock source for the AD7193. Either the on-chip 4.92 MHz clock or an external clock
can be used. The ability to use an external clock allows several AD7193 devices to be synchronized. Also,
50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7193.
CLK1
0
0
1
1
Fast settling filter. When this option is selected, the settling time equals one conversion time. In fast
settling mode, a first-order average and decimate block is included after the sinc filter. The data from the
sinc filter is averaged by 2, 8, or 16. The averaging reduces the output data rate for a given FS word;
however, the rms noise improves. The AVG1 and AVG0 bits select the amount of averaging. Fast settling
mode can be used for FS words less than 512 only. When the sinc
less than 256 when averaging by 16.
AVG1
0
0
1
1
Sinc
the sinc
For a given output data rate, f
a settling time of 4/f
50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no missing
codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc
better performance than the sinc
This bit must be programmed with a Logic 0 for correct operation.
Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit in
the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents
of the status register are transmitted along with the data for each data register read.
3
filter select bit. When this bit is cleared, the sinc
3
filter is used. The benefit of the sinc
AVG0
0
1
0
1
CLK0
0
1
0
1
MR20
DAT_STA(0)
MR12
CLK_DIV(0)
MR4
FS4(0)
ADC
Average
No averaging (fast settling mode disabled)
Average by 2
Average by 8
Average by 16
when chop is disabled. The sinc
ADC Clock Source
External crystal. The external crystal is connected from MCLK1 to MCLK2.
External clock. The external clock is applied to the MCLK2 pin.
Internal 4.92 MHz clock. Pin MCLK2 is tristated.
Internal 4.92 MHz clock. The internal clock is available on MCLK2.
Rev. C | Page 24 of 56
ADC
, the sinc
3
filter for rms noise and no missing codes.
MR19
CLK1(1)
MR11
Single(0)
MR3
FS3(0)
register. MR0 through MR23 indicate the bit locations, MR
denoting that the bits are in the mode register. MR23 denotes
the first bit of the data stream. The number in parentheses
indicates the power-on/reset default status of that bit. Any write
to the mode register resets the modulator and filter and sets the
RDY bit.
3
filter has a settling time of 3/f
3
filter compared to the sinc
4
filter is used (default value). When this bit is set,
4
MR18
CLK0(0)
MR10
REJ60(0)
MR2
FS2(0)
filter, due to its deeper notches, gives better
3
filter is selected, the FS word must be
ADC
4
filter is its lower settling time.
MR17
AVG1(0)
MR9
FS9(0)
MR1
FS1(0)
whereas the sinc
Data Sheet
FS0(0)
MR16
AVG0(0)
MR8
FS8(0)
MR0
4
filter has
4
filter gives