AD7699 Analog Devices, AD7699 Datasheet - Page 22

• Manufacturer Part Number: AD7699
• Description: 16-Bit, 8-Channel, 500 kSPS PulSAR ADC
• Manufacturer: Analog Devices

Specifications of AD7699

• Resolution (bits): 16bit
• # Chan: 8
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Bip,SE-Uni
• Ain Range: (Vref) p-p,4 V p-p,Bip (Vref) x 0.5,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP

AD7699
GENERAL TIMING WITHOUT A BUSY INDICATOR
Figure 35 details the timing for all three modes: reading/writing
during conversion, after conversion, and spanning conversion.
Note that the gating item for both CFG and data readback is at
the end of conversion (EOC). At the end of conversions (EOC),
if CNV is high, the busy indicator is disabled.
As detailed previously, the data access should occur up to safe
data reading/writing time, t
written to prior to EOC, it is discarded and the current
configuration remains. If the conversion result is not read out
fully prior to EOC, it is lost as the ADC updates SDO with the
PHASE
SDO
SDO
SDO
CNV
SCK
CNV
SCK
CNV
SCK
NOTES
1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.
DIN
DIN
DIN
A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK
IS ENABLED, A TOTAL OF 30 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.
POWER
UP
CONVERSION (n – 2)
1
t
DATA
t
XXX
XXX
CONV
16/30
DATA
t
CYC
. If the full CFG word was not
ACQUISITION
1
1
Figure 35. General Interface Timing for the AD7699 Without a Busy Indicator
START OF CONVERSION
(n – 1)
CFG (n)
(n – 2)
DATA
DATA
(n – 2)
16/30
(n – 2)
MSB
CFG (n)
CONVERSION (n – 1)
1
DATA (n – 2)
(n – 2)
DATA
16/30
CFG (n)
END OF CONVERSION (EOC)
16/30
Rev. A | Page 22 of 28
ACQUISITION
1
1
CFG (n + 1)
(n – 1)
(n)
DATA
(n – 1)
DATA
16/30
(n – 1)
MSB
MSB of the current conversion. For detailed timing, refer to
Figure 36 and Figure 37, which depict reading/writing spanning
conversion with all timing details, including setup, hold, and SCK.
When CNV is brought low after EOC, SDO is driven from high
impedance to the MSB. Falling SCK edges clock out bits starting
with MSB − 1.
The SCK can idle high or low depending on the clock polarity
(CPOL) and clock phase (CPHA) settings if SPI is used. A simple
solution is to use CPOL = CPHA = 0 as shown in Figure 35 with
SCK idling low.
CFG (n + 1)
CONVERSION (n)
1
DATA (n – 1)
CFG (n + 1)
(n – 1)
DATA
16/30
16/30
EOC
ACQUISITION
1
1
CFG (n + 2)
(n + 1)
DATA (n)
DATA (n)
16/30
MSB
(n)
CFG (n + 2)
CONVERSION (n + 1)
1
DATA (n)
CFG (n + 2)
DATA (n)
16/30
16/30
Data Sheet
EOC
ACQUISITION
1
1
DATA (n + 1)
CFG (n + 3)
CFG (n + 3)
(n + 2)
(n + 1)
DATA
(n + 1)
MSB