AD7699 Analog Devices, AD7699 Datasheet - Page 23

• Manufacturer Part Number: AD7699
• Description: 16-Bit, 8-Channel, 500 kSPS PulSAR ADC
• Manufacturer: Analog Devices

Specifications of AD7699

• Resolution (bits): 16bit
• # Chan: 8
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Bip,SE-Uni
• Ain Range: (Vref) p-p,4 V p-p,Bip (Vref) x 0.5,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP

Data Sheet
READ/WRITE SPANNING CONVERSION WITHOUT
A BUSY INDICATOR
This mode is used when the
using an SPI, serial port, or FPGA. The connection diagram is
shown in Figure 36, and the corresponding timing is given in
Figure 37. For SPI, the host should use CPHA = CPOL = 0.
Reading/writing spanning conversion is shown, which covers
all three modes detailed in the Digital Interface section. For this
mode, the host must generate the data transfer based on the
conversion time. For an interrupt driven transfer, refer to the
next section, which uses a busy indicator.
A rising edge on CNV initiates a conversion, forces SDO to
high impedance, and ignores data present on DIN. After a
conversion is initiated, it continues until completion irrespective
of the state of CNV. CNV must be returned high before the safe
data transfer time, t
sion time, t
After the conversion is complete, the
tion phase and powers down. When the host brings CNV low
after t
must enable the MSB of CFG at this time (if necessary) to begin
ACQUISITION
CONV
(n – 1)
CNV
SDO
SCK
DIN
(max), the MSB is enabled on SDO. The host also
CONV
, to avoid generation of the busy signal indicator.
t
DIS
DATA
t
SCKH
CONVERSION (n – 1)
, and then held high beyond the conver-
t
SCKL
t
END DATA (n – 2)
EN
t
DATA
CFG
LSB
14
END CFG (n)
t
AD7699
SCK
>
t
LSB + 1
t
CONV
15
X
CONV
AD7699
16/
30
LSB
is connected to any host
X
Figure 37. Serial Interface Timing for the
Figure 36. Connection Diagram for the
NOTES
1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF.
15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
t
DIS
enters the acquisi-
RETURN CNV HIGH
(QUIET
TIME)
FOR NO BUSY
UPDATE (n)
CFG/SDO
t
CYC
AD7699
t
CLSCK
t
EN
FOR SPI USE CPHA = 0, CPOL = 0.
SDO
SCK
CNV
DIN
MSB
CFG
MSB
Rev. A | Page 23 of 28
1
t
SDIN
BEGIN CFG (n + 1)
BEGIN DATA (n – 1)
MSB – 1
MSB – 1
CFG
2
ACQUISITION (n)
t
ACQ
t
HDIN
AD7699
AD7699
the CFG update. While CNV is low, both a CFG update and a
data readback take place. The first 14 SCK rising edges are used
to update the CFG, and the first 15 SCK falling edges clock out
the conversion results starting with MSB − 1. The restriction
for both configuring and reading is that they both must occur
before the t
of CFG[13:0] must be written, or they are ignored. In addition,
if the 16-bit conversion result is not read back before t
it is lost.
The SDO data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the 16
when CNV goes high (whichever occurs first), SDO returns to
high impedance.
If CFG readback is enabled, the CFG associated with the conver-
sion result is read back MSB first following the LSB of the
conversion result. A total of 30 SCK falling edges is required to
return SDO to high impedance if this is enabled.
SCK
SS
MISO
MOSI
DIGITAL HOST
t
t
HSDO
DSDO
Without a Busy Indicator
Without a Busy Indicator
DATA
time of the next conversion elapses. All 14 bits
t
t
EN
CNVH
t
DIS
CONVERSION (n)
END DATA (n – 1)
END CFG (n + 1)
CFG
LSB
14
t
DATA
LSB + 1
15
X
th
t
CONV
SEE NOTE
(or 30
16/
30
LSB
X
SEE NOTE
th
) SCK falling edge, or
t
RETURN CNV HIGH
DIS
(QUIET
TIME)
FOR NO BUSY
UPDATE (n + 1)
CFG/SDO
DATA
AD7699
ACQUISITION
(n + 1)
elapses,