AD7699 Analog Devices, AD7699 Datasheet - Page 25

• Manufacturer Part Number: AD7699
• Description: 16-Bit, 8-Channel, 500 kSPS PulSAR ADC
• Manufacturer: Analog Devices

Specifications of AD7699

• Resolution (bits): 16bit
• # Chan: 8
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Bip,SE-Uni
• Ain Range: (Vref) p-p,4 V p-p,Bip (Vref) x 0.5,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP

Data Sheet
READ/WRITE SPANNING CONVERSION WITH A
BUSY INDICATOR
This mode is used when the
using an SPI, serial port, or FPGA with an interrupt input. The
connection diagram is shown in Figure 39, and the
corresponding timing is given in Figure 40. For SPI, the host
should use CPHA = CPOL = 1. Reading/writing spanning
conversion is shown, which covers all three modes detailed in
the Digital Interface section.
A rising edge on CNV initiates a conversion, forces SDO to
high impedance, and ignores data present on DIN. After a
conversion is initiated, it continues until completion irrespec-
tive of the state of CNV. CNV must be returned low before the
safe data transfer time, t
conversion time, t
When the conversion is complete, SDO transitions from high
impedance to low with a pull-up to VIO, which can be used to
interrupt the host to begin data transfer.
After the conversion is complete, the
acquisition phase and power-down. The host must enable the
MSB of CFG at this time (if necessary) to begin the CFG
CONVERSION
CNV
SDO
SCK
DIN
(n – 1)
CONV
t
SCKH
END DATA (n – 2)
, to generate the busy signal indicator.
t
SCKL
END CFG (n)
DATA
CONVERSION (n – 1)
t
15
DATA
X
t
SCK
, and then held low beyond the
AD7699
16
LSB
X
+ 1
17/
31
X
LSB
AD7699
is connected to any host
Figure 40. Serial Interface Timing for the
Figure 39. Connection Diagram for the
NOTES
1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF.
t
DIS
16 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.
30 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.
ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.
OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW.
(QUIET
TIME)
enters the
t
UPDATE (n)
EN
t
CFG/SDO
CYC
AD7699
BEIGN CFG (n + 1)
FOR SPI USE CPHA = 1, CPOL = 1.
CFG
MSB
MSB
SDO
CNV
SCK
1
DIN
t
Rev. A | Page 25 of 28
SDIN
BEGIN DATA (n – 1)
MSB –1
CFG
MSB
t
– 1
HDIN
ACQUISITION (n)
2
t
VIO
ACQ
t
t
HSDO
DSDO
AD7699
MISO
IRQ
SS
MOSI
SCK
AD7699
update. While CNV is low, both a CFG update and a data
readback take place. The first 14 SCK rising edges are used to
update the CFG register, and the first 16 SCK falling edges clock
out the conversion results starting with the MSB. The restriction
for both configuring and reading is that they both occur before
the t
CFG[13:0] must be written or they are ignored. Also, if the 16-bit
conversion result is not read back before t
The SDO data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 17
SDO returns to high impedance. Note that, if the optional SCK
falling edge is not used, the busy feature cannot be detected if
the LSB for the conversion is low.
If CFG readback is enabled, the CFG register associated with
the conversion result (n − 1) is read back MSB first following
the LSB of the conversion result. A total of 31 SCK falling edges
is required to return SDO to high impedance if this is enabled.
DIGITAL HOST
DATA
with a Busy Indicator
with a Busy Indicator
time elapses for the next conversion. All 14 bits of
t
t
CNVH
EN
t
DIS
END DATA (n – 1)
END CFG (n + 1)
t
CONVERSION (n)
15
X
DATA
t
CONV
16
LSB
SEE NOTE
X
+ 1
SEE NOTE
17/
31
LSB
X
DATA
t
DIS
th
SCK falling edge,
(QUIET
TIME)
UPDATE (n + 1)
elapses, it is lost.
t
EN
CFG/SDO
ACQUISITION
AD7699
(n + 1)