AD7851 Analog Devices, AD7851 Datasheet - Page 15

• Manufacturer Part Number: AD7851
• Description: 14-Bit, 333 kSPS, Serial Sampling A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7851

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 333kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

CIRCUIT INFORMATION
The AD7851 is a fast, 14-bit single-supply ADC. The part
requires an external 6/7 MHz master clock (CLKIN), two
C
power supply decoupling capacitors. The part provides the user
with track-and-hold, on-chip reference, calibration features,
ADC, and serial interface logic functions on a single chip. The
ADC section of the AD7851 consists of a conventional succes-
sive approximation converter based around a capacitor DAC.
The AD7851 accepts an analog input range of 0 V to +V
where the reference can be tied to V
the part is buffered on-chip.
A major advantage of the AD7851 is that a conversion can be
initiated in software as well as applying a signal to the CONVST
pin. Another innovative feature of the AD7851 is self-calibration
on power-up, which is initiated having a capacitor from the
CAL pin to AGND, to give superior dc accuracy (see the
Automatic Calibration on Power-On section). The part is avail-
able in a 24-lead SSOP package which offers the user consider-
able space-saving advantages over alternative solutions.
CONVERTER DETAILS
The master clock for the part must be applied to the CLKIN
pin. Conversion is initiated on the AD7851 by pulsing the
CONVST input or by writing to the control register and setting
the CONVST bit to 1. On the rising edge of CONVST (or at
the end of the control register write operation), the on-chip
track-and-hold goes from track to hold mode. The falling edge
of the CLKIN signal which follows the rising edge of the
CONVST signal initiates the conversion, provided the rising
edge of CONVST occurs at least 10 ns typically before this
CLKIN edge. The conversion cycle will take 18.5 CLKIN peri-
ods from this CLKIN falling edge. If the 10 ns setup time is not
met, the conversion will take 19.5 CLKIN periods. The maxi-
REV. B
REF
capacitors, a CONVST signal to start conversion, and
ANALOG (5V)
ANALOG (5V)
AUTO CAL ON
POWER-UP
SUPPLY
SUPPLY
0V TO V
UNIPOLAR RANGE
REFERENCE
EXTERNAL
OPTIONAL
0.01 F
0.1 F
INPUT
REF
DV
DD
10 F
AD1584/REF198
470nF
0.01 F
10 F
0.1 F
AIN(+)
AIN(–)
AMODE
C
POLARITY
AGND
DGND
C
SLEEP
CAL
REF2
REF1
0.01 F
DD
AV
AD7851
REF
. The reference input to
DD
IN
/REF
DV
0.1 F
DD
OUT
CONVST
INTERNAL/
EXTERNAL
REFERENCE
0.1 F
CLKIN
SYNC
DOUT
SCLK
SM1
SM2
DIN
Figure 10. Typical Circuit
DD
SERIAL DATA OUTPUT
FRAME SYNC OUTPUT
SERIAL CLOCK OUTPUT
MASTER
CLOCK
SELECTION BITS
INPUT
OSCILLATOR
SERIAL MODE
7MHz/6MHz
–15–
mum specified conversion time is 3.25 µs (6 MHz ) and 2.8 µs
(7 MHz) for the A and K Grades, respectively, for the AD7851
(19.5 t
completed, the BUSY output goes low, and then the result of
the conversion can be read by accessing the data through the
edge of serial interface. To obtain optimum performance from
the part, the read operation should not occur during the conver-
sion or 500 ns prior to the next CONVST rising edge. How-
ever, the maximum throughput rates are achieved by reading/
writing during conversion, and reading/writing during conver-
sion is likely to degrade the signal-to-(noise + distortion) by
only 0.5 dBs. The AD7851 can operate at throughput rates up
to 333 kHz. For the AD7851, a conversion takes 19.5 CLKIN
periods; 2 CLKIN periods are needed for the acquisition time
giving a full cycle time of 3.59 µs (= 279 kHz, CLKIN = 6 MHz)
for the K grade and 3.08 µs (= 325 kHz, CLKIN = 7 MHz) for
the A grade.
TYPICAL CONNECTION DIAGRAM
Figure 10 shows a typical connection diagram for the AD7851.
The DIN line is tied to DGND so that no data is written to the
part. The AGND and the DGND pins are connected together
at the device for good noise suppression. The CAL pin has a
0.01 µF capacitor to enable an automatic self-calibration on
power-up. The SCLK and SYNC are configured as outputs by
having SM1 and SM2 at DV
in a 16-bit word with 2 leading zeros followed by the MSB of
the 14-bit result. Note that after the AV
the part will require approximately 150 ms for the internal refer-
ence to settle and for the automatic calibration on power-up to
be completed.
For applications where power consumption is a major concern, the
SLEEP pin can be connected to DGND. (See the Power-Down
Options section for more detail on low power applications.)
DV
333kHz/285kHz PULSE
CLKIN,
DD
GENERATOR
CLKIN = 6 MHz/7 MHz). When a conversion is
DIN AT DGND
=> NO WRITING
CONVERSION
START INPUT
TO DEVICE
CH1
CH2
CH3
CH4
DD
. The conversion result is output
2 LEADING ZEROS
OSCILLOSCOPE
FOR ADC DATA
DD
and DV
AD7851
DD
power up,