AD7851 Analog Devices, AD7851 Datasheet - Page 9

• Manufacturer Part Number: AD7851
• Description: 14-Bit, 333 kSPS, Serial Sampling A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7851

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 333kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

REV. B
Pin No. Mnemonic Description
1
2
3
4
5
6, 12
7
8
9
10
11
13
14
15
16
17
18
19
20
21
22
23
24
CONVST
BUSY
SLEEP
REF
REF
AV
AGND
C
C
AIN(+)
AIN(–)
NC
AMODE
POLARITY Serial Clock Polarity. This pin determines the active edge of the serial clock (SCLK). Toggling this pin will
SM1
SM2
CAL
DV
DGND
DOUT
DIN
CLKIN
SCLK
SYNC
REF1
REF2
DD
DD
IN
OUT
/
Convert Start. Logic input. A low-to-high transition on this input puts the track-and-hold into its hold
mode and starts conversion. When this input is not used, it should be tied to DV
Busy Output. The busy output is triggered high by the falling edge of CONVST or rising edge of CAL and
remains high until conversion is completed. BUSY is also used to indicate when the AD7851 has completed
its on-chip calibration sequence.
Sleep Input/Low Power Mode. A Logic 0 initiates a sleep and all circuitry is powered down, including the
internal voltage reference, provided there is no conversion or calibration being performed. Calibration data
is retained. A Logic 1 results in normal operation. See Power-Down section for more details.
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
reference source for the analog-to-digital converter. The nominal reference voltage is 4.096 V and this appears
at the pin. This pin can be overdriven by an external reference or can be taken as high as AV
pin is tied to AV
be tied to AV
Analog Positive Supply Voltage, 5.0 V ± 5%.
Analog Ground. Ground reference for track and hold, reference, and DAC.
Reference Capacitor (0.1 µF ceramic disc in parallel with a 470 nF tantalum). This external capacitor is
used as a charge source for the internal DAC. The capacitor should be tied between the pin and AGND.
Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip
reference. The capacitor should be tied between the pin and AGND.
Analog Input. Positive input of the pseudo-differential analog input. Cannot go below AGND or above
AV
Analog Input. Negative input of the pseudo-differential analog input. Cannot go below AGND or above
AV
No Connect Pin.
Analog Mode Pin. This pin allows two different analog input ranges to be selected. A Logic 0 selects range
0 to V
cannot go below AGND. A Logic 1 selects range –V
+V
allow AIN(+) to go from 0 V to +V
reverse the active edge of the serial clock (SCLK). A Logic 1 means that the serial clock (SCLK) idles high
and a Logic 0 means that the serial clock (SCLK) idles low. It is best to refer to the timing diagrams and
Table IX for the SCLK active edges.
Serial Mode Select Pin. This pin is used in conjunction with the SM2 pin to give different modes of opera-
tion as described in Table X.
Serial Mode Select Pin. This pin is used in conjunction with the SM1 pin to give different modes of opera-
tion as described in Table X.
Calibration Input. This pin has an internal pull-up current source of 0.15 µA. A Logic 0 on this pin resets all
calibration control logic and initiates a calibration on its rising edge. There is the option of connecting a 10 nF
capacitor from this pin to DGND to allow for an automatic self-calibration on power-up. This input overrides
all other internal operations. If the autocalibration is not required, then this pin should be tied to a logic high.
Digital Supply Voltage, 5.0 V ± 5%.
Digital Ground. Ground reference point for digital circuitry.
Serial Data Output. The data output is supplied to this pin as a 16-bit serial word.
Serial Data Input. The data to be written is applied to this pin in serial form (16-bit word). This pin can act as
an input pin or as a input and output pin depending on the serial interface mode the part is in (see Table X).
Master Clock Signal for the Device (6 MHz or 7 MHz). Sets the conversion and calibration times.
Serial Port Clock. Logic input/output. The SCLK pin is configured as an input or output, dependent on the
type of serial data transmission (self-clocking or external-clocking) that has been selected by the SM1 and
SM2 pins. The SCLK idles high or low depending on the state of the POLARITY pin.
This pin can be an input level triggered active low (similar to a chip select in one case and to a frame sync
in the other) or an output (similar to a frame sync) pin depending on SM1, SM2 (see Table X).
DD
DD
REF
REF
/2). In this case, AIN(+) cannot go below AGND so that AIN(–) needs to be biased to +V
at any time and cannot go below AIN(–) when the unipolar input range is selected.
at any time.
(i.e., AIN(+) – AIN(–) = 0 to V
DD
.
DD
, or when an externally applied reference approaches V
PIN FUNCTION DESCRIPTIONS
REF
–9–
V.
REF
). In this case, AIN(+) cannot go below AIN(–) and AIN(–)
REF
/2 to +V
REF
/2 (i.e., AIN(+) – AIN(–) = –V
DD
, then the C
DD
.
REF1
DD
AD7851
. When this
pin should also
REF
REF
/2 to
/2 to