AD7851 Analog Devices, AD7851 Datasheet - Page 26

• Manufacturer Part Number: AD7851
• Description: 14-Bit, 333 kSPS, Serial Sampling A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7851

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 333kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

AD7851
Mode 2 (3-Wire SPI/QSPI Interface Mode)
Default Interface Mode
Figure 35 shows the timing diagram for Interface Mode 2 which
is the SPI/QSPI interface mode. Here the SYNC input is active
low and may be pulsed or tied permanently low. If SYNC is
permanently low, 16 clock pulses must be applied to the SCLK
pin for the part to operate correctly, and with a pulsed SYNC
input a continuous SCLK may be applied provided SYNC is
low for only 16 SCLK cycles. In Figure 35, the SYNC going
low disables the three-state on the DOUT pin. The first falling
edge of the SCLK after the SYNC going low clocks out the first
leading zero on the DOUT pin. The DOUT pin is three-stated
again a time t
the data input has to be set up a time t
edge as the part samples the input data on the SCLK rising edge
in this case. The POLARITY pin may be used to change the
SCLK edge which the data is sampled on and clocked out on. If
resetting the interface is required, the SYNC must be taken high
and then low.
Figure 36. QSPI Mode 3 Timing Diagram for Read/Write Operation with SYNC Input Edge Triggered (SM1 = 0, SM2 = 1)
Figure 35. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation with DIN Input, DOUT Output, and SYNC Input
(SM1 = SM2 = 0)
DOUT (O/P)
DOUT (O/P)
SYNC (I/P)
SCLK (I/P)
SYNC (I/P)
SCLK (I/P)
DIN (I/P)
12
DIN (I/P)
after the SYNC goes high. With the DIN pin,
POLARITY PIN
LOGIC HIGH
POLARITY PIN
LOGIC HIGH
THREE-STATE
THREE-STATE
t
t
5
5
t
t
3
3
DB15
DB15
t
t
7
7
t
t
t
t
30/0.4 t
3
6
1
1
3
6
= –0.4 t
= 45ns MAX, t
= –0.4 t
= 45ns MAX, t
DB15
t
DB15
t
6
6
7
t
t
8
8
before the SCLK rising
SCLK
CLKIN
CLKIN
DB14
DB14
= ns MIN/MAX (CONTINUOUS SCLK)
2
2
MIN (NONCONTINUOUS SCLK) ±0.4 t
DB14
DB14
MIN (NONCONTINUOUS SCLK) ±0.4 t
7
7
= 30ns MIN, t
= 30ns MIN, t
t
t
9
9
DB13
DB13
t
t
10
10
3
3
DB13
DB13
8
8
= 20ns MIN, t
= 20ns MIN, t
DB12
DB12
–26–
4
4
DB12
DB12
Mode 3 (QSPI Interface Mode)
Figure 36 shows the timing diagram for Interface Mode 3. In
this mode, the DSP is the master and the part is the slave. Here
the SYNC input is edge triggered from high to low, and the 16
clock pulses are counted from this edge. Because the clock
pulses are counted internally, the SYNC signal does not have to
go high after the 16th SCLK rising edge as shown by the dotted
SYNC line. Thus a frame sync that gives a high pulse of one
SCLK cycle minimum duration at the beginning of the read/
write operation may be used. The rising edge of SYNC enables
the three-state on the DOUT pin. The falling edge of SYNC
disables the three-state on the DOUT pin, and data is clocked
out on the falling edge of SCLK. Once SYNC goes high, the
three-state on the DOUT pin is enabled. The data input is
sampled on the rising edge of SCLK and thus has to be valid a
time t
used to change the SCLK edge which the data is sampled on
and clocked out on. If resetting the interface is required, the
SYNC must be taken high and then low.
11
DB11
DB11
11
= 30ns MIN
5
5
= 30ns MIN (NONCONTINUOUS SCLK),
7
t
DB11
DB11
t
6
before this rising edge. The POLARITY pin may be
6
SCLK
SCLK
DB10
DB10
MIN/MAX (CONTINUOUS SCLK),
MIN/MAX (CONTINUOUS SCLK),
6
6
DB10
DB10
t
t
8
8
DB0
DB0
16
16
DB0
DB0
t
t
11
11
THREE-STATE
THREE-STATE
t
t
12
12
REV. B