AD7851 Analog Devices, AD7851 Datasheet - Page 5

• Manufacturer Part Number: AD7851
• Description: 14-Bit, 333 kSPS, Serial Sampling A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7851

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 333kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

TIMING SPECIFICATIONS
Descriptions that refer to SCLK↑ (rising) or SCLK↓ (falling) edges are with the POLARITY pin HIGH. For the POLARITY pin
LOW, then the opposite edge of SCLK will apply.
Parameter
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
5
6
7
8
9
Specifications subject to change without notice.
REV. B
CLKIN
SCLK
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
Mark/space ratio for the master clock input is 40/60 to 60/40.
For Interface Modes 1, 2, 3, the SCLK maximum frequency will be 10 MHz. For Interface Modes 4 and 5, the SCLK will be an output and the frequency will be f
The CONVST pulse width will only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power-
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
For self-clocking mode (Interface Modes 4, 5), the nominal SCLK high and low times will be 0.5 t
The time t
The typical time specified for the calibration times is for a master clock of 6 MHz.
1
2
CONVERT
3
4
5
5A
6
7
8
9
10
11
11A
12
13
14
15
16
CAL
CAL1
CAL2
DELAY
Table X and timing diagrams for different interface modes and calibration.
Down section).
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that t
relinquish time of the part and is independent of the bus loading.
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true
delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed , the user can drive the DIN line knowing
that a bus conflict will not occur.
The time t
4
5
5
6
6
7
8
5
9
9
9
3
2
12
14
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
Limit at T
(A, K Versions)
500
7
10
f
100
50
3.25
–0.4 t
± 0.4 t
0.6 t
30
30
45
30
20
0.4 t
0.4 t
30
30/0.4 t
50
50
90
50
2.5 t
2.5 t
41.7
37.04
4.63
65
CLK IN
SCLK
SCLK
SCLK
CLKIN
CLKIN
SCLK
SCLK
SCLK
MIN
, T
MAX
1
(AV
DD
Unit
kHz min
MHz max
MHz max
MHz max
ns min
ns max
µs max
ns min
ns min/max
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min/max
ns max
ns max
ns max
ns max
ns max
ns max
ms typ
ms typ
ms typ
ns max
= DV
DD
= 5.0 V
5%; f
Description
Master Clock Frequency
Interface Modes 1, 2, 3 (External Serial Clock)
Interface Modes 4, 5 (Internal Serial Clock)
CONVST Pulse Width
CONVST↓ to BUSY↑ Propagation Delay
Conversion Time = 20 t
SYNC↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input)
SYNC↓ to SCLK↓ Setup Time (Continuous SCLK Input)
SYNC↓ to SCLK↓ Setup Time, Interface Mode 4 Only
Delay from SYNC↓ until DOUT Three-State Disabled
Delay from SYNC↓ until DIN Three-State Disabled
Data Access Time after SCLK↓
Data Setup Time prior to SCLK↑
Data Valid to SCLK Hold Time
SCLK High Pulse Width (Interface Modes 4 and 5)
SCLK Low Pulse Width (Interface Modes 4 and 5)
SCLK↑ to SYNC↑ Hold Time (Noncontinuous SCLK)
(Continuous SCLK) Does Not Apply to Interface Mode 3
SCLK↑ to SYNC↑ Hold Time
Delay from SYNC↑ until DOUT Three-State Enabled
Delay from SCLK↑ to DIN Being Configured as Output
Delay from SCLK↑ to DIN Being Configured as Input
CAL↑ to BUSY↑ Delay
CONVST↓ to BUSY↑ Delay in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent
(250026 t
Internal DAC Plus System Full-Scale Calibration Time, Master Clock
Dependent (222228 t
System Offset Calibration Time, Master Clock Dependent
(27798 t
Delay from CLK to SCLK
–5–
CLKIN
= 6 MHz, T
CLKIN
CLKIN
)
)
SCLK
A
= T
= 0.5 t
CLKIN
MIN
12
CLKIN
as quoted in the timing characteristics is the true bus
to T
CLKIN
)
DD
MAX
) and timed from a voltage level of 1.6 V. See
.
, unless otherwise noted.)
AD7851
CLKIN
.