AD7858 Analog Devices, AD7858 Datasheet - Page 25

• Manufacturer Part Number: AD7858
• Description: 3 V to 5 V Single Supply, 200 kSPS, 8-Channel, 12-Bit, Serial Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7858

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 200kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC

Mode 2 (3-Wire SPI/QSPI Interface Mode)
This is the DEFAULT INTERFACE MODE.
In Figure 33 below we have the timing diagram for interface
Mode 2 which is the SPI/QSPI interface mode. Here the SYNC
input is active low and may be pulsed or tied permanently low.
If SYNC is permanently low, 16 clock pulses must be applied to
the SCLK pin for the part to operate correctly, otherwise with a
pulsed SYNC input a continuous SCLK may be applied pro-
vided SYNC is low for only 16 SCLK cycles. In Figure 33 the
DOUT (O/P)
SCLK (I/P)
POLARITY PIN LOGIC HIGH
SYNC (I/P)
DIN (I/P)
THREE-STATE
t
5
t
6
t
3
DB15
t
7
1
t
t
t
(CONTINUOUS SCLK) (5V/3V)
DB15
3
6
11
= –0.4
= 75/115ns MAX (5V/3V),
= 30/50ns MIN (NONCONTINUOUS SCLK) (5V/3V), (30/50)/0.4
DB14
t
t
SCLK
2
8
DB14
MIN (NONCONTINUOUS SCLK) 0.4
t
9
DB13
t
3
10
DB13
t
7
= 40/60ns MIN (5V/3V),
DB12
4
t
6
DB12
SYNC
SYNC going low disables the three-state on the DOUT pin.
The first falling edge of the SCLK after the SYNC going low
clocks out the first leading zero on the DOUT pin. The DOUT
pin is three-stated again a time t
With the DIN pin the data input has to be set up a time t
fore the SCLK rising edge as the part samples the input data on
the SCLK rising edge in this case. If resetting the interface is
required, the SYNC must be taken high and then low.
DB11
5
DB11
t
t
SCLK
8
DB10
t
8
= 20/30ns MIN (5V/3V),
6
ns MIN/MAX (CONTINUOUS SCLK),
DB10
t
SCLK
ns MIN/MAX
DB0
16
DB0
t
11
12
AD7858/AD7858L
after the SYNC goes high.
THREE-STATE
t
12
7
be-