AD5735 Analog Devices, AD5735 Datasheet - Page 33

• Manufacturer Part Number: AD5735
• Description: Quad Channel, 12-Bit, Serial Input, 4-20 mA & Voltage Output DAC with Dynamic Power Control
• Manufacturer: Analog Devices

Specifications of AD5735

• Resolution (bits): 12bit
• Dac Settling Time: 11µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: I or V Out
• Dac Input Format: SPI

Gain Register
The 12-bit gain register allows the user to adjust the gain of
each channel in steps of 1 LSB. To write to the gain register of
one DAC channel, set the DREG[2:0] bits to 010 (see Table 14).
To write the same gain code to all four DAC channels at the
same time, set the DREG[2:0] bits to 011. The gain register
coding is straight binary, as shown in Table 15. The default code
in the gain register is 0xFFFF. The maximum recommended
gain trim is approximately 50% of the programmed range to
maintain accuracy (for more information, see the Digital Offset
and Gain Control section).
Offset Register
The 12-bit offset register allows the user to adjust the offset
of each channel by −2048 LSB to +2047 LSB in steps of 1 LSB.
To write to the offset register of one DAC channel, set the
Table 14. Programming the Gain Register
R/W
0
Table 15. Gain Register Bit Descriptions
Gain Adjustment
+4096 LSB
+4095 LSB
…
1 LSB
0 LSB
Table 16. Programming the Offset Register
R/W
0
Table 17. Offset Register Bit Descriptions
Offset Adjustment
+2047 LSB
+2046 LSB
…
No Adjustment (Default)
…
−2047 LSB
−2048 LSB
Table 18. Programming the Clear Code Register
R/W
0
Data Sheet
DUT_AD1
DUT_AD1
DUT_AD1
Device address
Device address
Device address
DUT_AD0
DUT_AD0
DUT_AD0
G15
1
1
…
0
0
OF15
1
1
…
1
…
0
0
DREG2
0
DREG2
1
DREG2
1
G14
1
1
…
0
0
OF14
1
1
…
0
…
0
0
DREG1
1
DREG1
0
DREG1
1
Rev. A | Page 33 of 48
DREG0
0
DREG0
0
DREG0
0
G13 to G5
111111111
111111111
…
000000000
000000000
OF13
1
1
…
0
…
0
0
DREG[2:0] bits to 100 (see Table 16). To write the same offset
code to all four DAC channels at the same time, set the DREG[2:0]
bits to 101. The offset register coding is straight binary, as shown in
Table 17. The default code in the offset register is 0x8000, which
results in zero offset programmed to the output (for more infor-
mation, see the Digital Offset and Gain Control section).
Clear Code Register
The 12-bit clear code register allows the user to set the clear
value of each channel. To configure a channel to be cleared
when the CLEAR pin is activated, set the CLR_EN bit in the
DAC control register for that channel (see Table 24). To write
to the clear code register, set the DREG[2:0] bits to 110 (see
Table 18). The default clear code is 0x0000 (for more informa-
tion, see the Asynchronous Clear section).
DAC_AD1
DAC_AD1
DAC_AD1
DAC channel address
DAC channel address
DAC channel address
OF12 to OF5
…
…
11111111
11111111
00000000
00000000
00000000
DAC_AD0
DAC_AD0
DAC_AD0
G4
1
0
…
1
0
OF4
1
0
…
0
…
1
0
D15 to D4
Gain adjustment
D15 to D4
Offset adjustment
D15 to D4
Clear code
G3 to G0
1111
1111
1111
1111
1111
OF3 to OF0
0000
0000
0000
0000
0000
0000
0000
AD5735
D3 to D0
1111
D3 to D0
0000
D3 to D0
0000