AD5735 Analog Devices, AD5735 Datasheet - Page 40

• Manufacturer Part Number: AD5735
• Description: Quad Channel, 12-Bit, Serial Input, 4-20 mA & Voltage Output DAC with Dynamic Power Control
• Manufacturer: Analog Devices

Specifications of AD5735

• Resolution (bits): 12bit
• Dac Settling Time: 11µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: I or V Out
• Dac Input Format: SPI

AD5735
ASYNCHRONOUS CLEAR
CLEAR is an active high, edge sensitive input that allows the
output to be cleared to a preprogrammed 12-bit code. This code
is user-programmable via a per-channel 12-bit clear code register.
For a channel to be cleared, set the CLR_EN bit in the DAC
control register for that channel. If the clear function on a
channel is not enabled, the output remains in its current state,
independent of the level of the CLEAR pin.
When the CLEAR signal returns low, the relevant outputs remain
cleared until a new value is programmed to them.
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy environ-
ments, the
based on an 8-bit cyclic redundancy check (CRC-8). The device
controlling the
sequence using the following polynomial:
This value is added to the end of the data-word, and 32 bits are
sent to the
32-bit frame, it performs the error check when
If the error check is valid, the data is written to the selected register.
If the error check fails, the FAULT pin goes low and the PEC error
bit in the status register is set. After the status register is read,
FAULT returns high (assuming that there are no other faults),
and the PEC error bit is cleared automatically.
FAULT
Packet error checking can be used for transmitting and receiving
data packets. If status readback during a write is enabled, the PEC
values returned during the status readback operation should be
SYNC
SYNC
SCLK
SCLK
SDIN
SDIN
C(x) = x
MSB
AD5735
D23
MSB
AD5735
D31
32-BIT DATA TRANSFER WITH ERROR CHECKING
8
24-BIT DATA TRANSFER—NO ERROR CHECKING
+ x
AD5735
2
+ x
before SYNC goes high. If the
offers the option of packet error checking
UPDATE ON SYNC HIGH
1
Figure 76. PEC Timing
+ 1
24-BIT DATA
24-BIT DATA
should generate an 8-bit frame check
ONLY IF ERROR CHECK PASSED
LSB
LSB
UPDATE ON SYNC HIGH
D0
D8
IF ERROR CHECK FAILS
FAULT PIN GOES LOW
D7
SYNC goes high.
8-BIT CRC
AD5735
D0
sees a
Rev. A | Page 40 of 48
ignored. If status readback during a write is disabled, the user
can still use the normal readback operation to monitor status
register activity with PEC.
WATCHDOG TIMER
When enabled, an on-chip watchdog timer generates an alert
signal if 0x195 is not written to the software register within the
programmed timeout period. This feature is useful to ensure
that communication has not been lost between the MCU and
the
(that is, SDIN, SCLK, and SYNC ). If 0x195 is not received by
the software register within the timeout period, the ALERT pin
signals a fault condition. The ALERT pin is active high and can
be connected directly to the CLEAR pin to enable a clear in the
event that communication from the MCU is lost.
To enable the watchdog timer and set the timeout period (5 ms,
10 ms, 100 ms, or 200 ms), program the main control register
(see Table 21 and Table 22).
ALERT OUTPUT
The
active high CMOS output. The
watchdog timer. When enabled, the watchdog timer monitors
SPI communications. If 0x195 is not received by the software
register within the timeout period, the ALERT pin is activated.
INTERNAL REFERENCE
The
initial accuracy of ±5 mV maximum and a temperature coefficient
of ±10 ppm/°C maximum. The reference voltage is buffered and
is externally available for use elsewhere within the system.
EXTERNAL CURRENT SETTING RESISTOR
R
current conversion circuitry (see Figure 71). The stability of the
output current value over temperature is dependent on the stability
of the R
over temperature, the internal R
and an external, 15 kΩ, low drift resistor can be connected to
the R
via the DAC control register (see Table 24).
Table 1 provides the performance specifications for the
with both the internal R
resistor. The use of an external R
performance over the internal R
R
performance depends on the absolute value and temperature
coefficient of the resistor used. This directly affects the gain error
of the output and, thus, the total unadjusted error. To arrive at
the gain/TUE error of the output with a specific external R
resistor, add the absolute error percentage of the R
directly to the gain/TUE error of the
R
SET
SET
SET
AD5735
AD5735
AD5735
is an internal sense resistor that is part of the voltage-to-
resistor specifications assume an ideal resistor; the actual
resistor, as shown in Table 1 (expressed in % FSR).
SET_x
SET
pin of the AD5735. The external resistor is selected
value. To improve the stability of the output current
and that the datapath lines are working properly
is equipped with an ALERT pin. This pin is an
contains an integrated 5 V voltage reference with
SET
resistor and an external, 15 kΩ R
AD5735
SET
SET
SET
resistor, R1, can be bypassed
resistor option. The external
resistor allows for improved
AD5735
also has an internal
with the external
Data Sheet
SET
resistor
AD5735
SET
SET