AD5061 Analog Devices, AD5061 Datasheet

no-image

AD5061

Manufacturer Part Number
AD5061
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD5061

Resolution (bits)
16bit
Dac Update Rate
1.3MSPS
Dac Settling Time
4µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
Ser,SPI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD5061BRJZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD5061BRJZ-2REEL7
Manufacturer:
ADI
Quantity:
10 106
Part Number:
AD5061YRJZ-1500RL7
Manufacturer:
ADI
Quantity:
500
FEATURES
Single 16-bit DAC, 4 LSB INL
Power-on reset to midscale or zero-scale
Guaranteed monotonic by design
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
Small 8-lead SOT-23 package, low power
Fast settling time of 4 μs typically
2.7 V to 5.5 V power supply
Low glitch on power-up
SYNC interrupt facility
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5061, a member of ADI’s nanoDAC family, is a low
power, single 16-bit buffered voltage-out DAC that operates
from a single 2.7 V to 5.5 V supply. The part offers a relative
accuracy specification of ±4 LSB and operation is guaranteed
monotonic with a ±1 LSB DNL specification. The part uses a
versatile 3-wire serial interface that operates at clock rates
up to 30 MHz, and is compatible with standard SPI®, QSPI™,
MICROWIRE™, and DSP interface standards. The reference for
the AD5061 is supplied from an external V
buffer is also provided on-chip. The part incorporates a power-
on reset circuit that ensures the DAC output powers up to mid-
scale or zero scale and remains there until a valid write takes
place to the device. The part contains a power-down feature
that reduces the current consumption of the device to typically
330 nA at 5 V and provides software-selectable output loads
while in power-down mode. The part is put into power-down
mode over the serial interface. Total unadjusted error for the
part is <3 mV. This part exhibits very low glitch on power-up.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
REF
pin. A reference
SPI Interface 2.7 V to 5.5 V, in an SOT-23
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
Table 1. Related Devices
Part No.
AD5062
AD5063
AD5040/AD5060
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
SYNC
Available in a small 8-lead SOT-23 package.
16-bit resolution, 4 LSB INL.
Low glitch on power-up.
High speed serial interface with clock speeds up to 30 MHz.
Three power-down modes available to the user.
Reset to known output voltage (midscale or zero scale).
CONTROL
POWER-ON
REGISTER
LOGIC
INPUT
RESET
SCLK
DAC
FUNCTIONAL BLOCK DIAGRAM
DIN
©2005–2011 Analog Devices, Inc. All rights reserved.
16-Bit V
REF(+)
Description
2.7 V to 5.5 V, 16-bit nanoDAC D/A,
1 LSB INL, SOT-23
2.7 V to 5.5 V, 16-bit nanoDAC D/A,
1 LSB INL, MSOP
2.7 V to 5.5 V, 14-bit/16-bit nanoDAC D/A,
1 LSB INL, SOT-23
DAC
CONTROL LOGIC
V
POWER-DOWN
BUF
DACGND
REF
Figure 1.
OUT
OUTPUT
BUFFER
V
DD
nanoDAC
AD5061
AD5061
NETWORK
www.analog.com
RESISTOR
V
AGND
OUT

Related parts for AD5061

AD5061 Summary of contents

Page 1

... Programmable voltage and current sources Programmable attenuators GENERAL DESCRIPTION The AD5061, a member of ADI’s nanoDAC family low power, single 16-bit buffered voltage-out DAC that operates from a single 2 5.5 V supply. The part offers a relative accuracy specification of ±4 LSB and operation is guaranteed monotonic with a ± ...

Page 2

... AD5061 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Terminology .................................................................................... 14 Theory of Operation ...................................................................... 15 DAC Architecture....................................................................... 15 REVISION HISTORY 5/11—Rev Rev. B Changes to Data Sheet Title and Product Highlights Section.... 1 Changes to Ordering Guide .......................................................... 20 1/06— ...

Page 3

... L L DAC code = full-scale, output shorted to GND 25°C A DAC code = zero-scale, output shorted 25°C A Time to exit power-down mode to normal th mode of AD5061, 24 clock edge to 90% of DAC final value, output unloaded V ±10%, DAC code = full-scale DD Output frequency = 10 kHz Zero-scale loaded , DD ...

Page 4

... AD5061 Parameter LOGIC INPUTS 5 Input Current Input Low Voltage ( Input High Voltage ( Pin Capacitance POWER REQUIREMENTS (Normal Mode 2 5 (All Power-Down Modes 2 5 Temperature range for B grade: −40°C to +85°C, typical at 25°C; temperature range for Y grade: −40°C to +125°C. ...

Page 5

... SCLK falling edge to SYNC rising edge ns min Minimum SYNC high time ns min SYNC rising edge to next SCLK fall ignore ) and timed from a voltage level D22 D2 D1 Figure 2. Timing Diagram Rev Page )/ D23 D22 AD5061 ...

Page 6

... AD5061 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter V to GND DD Digital Input Voltage to GND V to GND OUT V to GND REF Operating Temperature Range Industrial (B Grade) Extended Automotive Temperature Range (Y Grade) Storage Temperature Range Maximum Junction Temperature SOT-23 Package Power Dissipation θ Thermal Impedance JA θ ...

Page 7

... Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates MHz. DIN 1 8 SCLK AD5061 V 2 TOP VIEW 7 SYNC DD (Not to Scale) DACGND REF V AGND 4 5 OUT Figure 3. Pin Configuration Rev Page AD5061 should be decoupled to GND. DD ...

Page 8

... AD5061 TYPICAL PERFORMANCE CHARACTERISTICS 1 25° 4.096V DD REF 1.2 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 160 10160 20160 30160 40160 DAC CODE Figure 4. Typical INL Plot 0. 25° 4.096V DD REF 0.12 0.10 0.08 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 –0.10 –0.12 – ...

Page 9

... Figure 13. Supply Current vs. Temperature T = 25° 5.5V 4.096V DD REF V = 3.0V 2.5V DD REF 10000 20000 30000 40000 50000 60000 DAC CODE Figure 14. Supply Current vs. Digital Input Code V = 2.5V REF T = 25°C A CODE = MIDSCALE 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) Figure 15. Supply Current vs. Supply Voltage AD5061 120 140 70000 6.0 ...

Page 10

... AD5061 1 5.5V 4.096V DD REF 1 2.7V 2.0V DD REF 1.4 1.2 1.0 0.8 OFFSET ERROR @ V = 5.5V DD 0.6 0.4 0.2 OFFSET ERROR @ V 0 –0.2 –0.4 –0.6 –40 – TEMPERATURE (°C) Figure 16. Offset vs. Temperature 24TH CLOCK FALLING CH1 = SCLK CH2 = V OUT CH2 50mV/DIV CH1 2V/DIV TIME BASE 400ns/DIV Figure 17. Digital-to-Analog Glitch Impulse; See Figure 21 ...

Page 11

... MORE Rev Page CH1 = V DD CH2 = V OUT = 4.096V REF DD = 25°C Figure 25. Hardware Power-Down Glitch CH1 = SCLK CH2 = SYNC CH3 = V OUT = 4.096V REF DD CH4 = TRIGGER Figure 26. Exiting Software Power-Down Glitch REFERENCE VOLTAGE (V) Figure 27. V Headroom vs. Reference Voltage. DD AD5061 5.3 5.5 ...

Page 12

... AD5061 5. 5. 25°C T 5.00 A DAC = FULL-SCALE 4.95 4.90 4.85 4.80 4.75 4.70 4.65 4.60 4.55 4.70 4.72 4.74 4.76 4.78 4.80 4.82 4.84 4.86 4.88 4.90 4.92 4.94 4.96 4.98 5.00 V (V) REF Figure 28. Typical Output Voltage vs. Reference Voltage 5.005 REF T = 25°C A 5.000 4.995 4.990 4.985 4.980 4.975 5.50 5.45 5.40 5.35 5.30 5.25 5.20 V (V) DD Figure 29. Typical Output Voltage vs. Supply Voltage ZERO-SCALE 1kΩ TO GND CH4 50.0mV M4.00µs Figure 30. Typical Glitch upon Entering Software Power-Down to Zero-Scale Figure 31 ...

Page 13

... Rev Page AD5061 4.096V REF 10% TO 90% RISE TIME = 0.688µs SLEW RATE = 1.16V/µs 2.04V DAC OUTPUT 1.04V –8µs –6µs –4µs –2µs 0 2µs 4µs 6µs Figure 36. Typical Output Slew Rate 8µ ...

Page 14

... DAC register. Ideally, the output should The zero-code error is always positive in the AD5061 because the output of the DAC cannot go below 0 V. This is due to a combination of the offset errors in the DAC and output amplifier. Zero-code error is expressed in mV. ...

Page 15

... THEORY OF OPERATION The AD5061 is a single 16-bit, serial input, voltage output DAC. It operates from supply voltages of 2 5.5 V. Data is writ- ten to the AD5061 in a 24-bit word format, via a 3-wire serial interface. The AD5061 incorporates a power-on reset circuit that ensures the DAC output powers up to zero-scale or midscale. The device also has a software power-down mode pin that reduces the typical current consumption to less than 1 μ ...

Page 16

... V see Figure 19. MICROPROCESSOR INTERFACING AD5061-to-ADSP-2101/ADSP-2103 Interface Figure 40 shows a serial interface between the AD5061 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in the SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, 16-bit word length ...

Page 17

... The 80C51/80L51 out- puts the serial data in a format that has the LSB first. The AD5061 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account. 80C51/80L51 ...

Page 18

... Precision voltage references, such as the ADR435, produce low output noise in the 0 region. Table 7 shows examples of recommended precision references for use as a supply to the AD5061. Table 7. Precision References Part List for the AD5061 . The Initial REF Accuracy Part No ...

Page 19

... The printed circuit board containing the AD5061 should have separate analog and digital sections, each having its own area of the board. If the AD5061 system where other devices require an AGND-to-DGND connection, then the connection should be made at one point only. This ground point should be as close as possible to the AD5061 ...

Page 20

... AD5061BRJZ-1500RL7 −40°C to +85°C AD5061BRJZ-2REEL7 −40°C to +85°C AD5061BRJZ-2500RL7 −40°C to +85°C AD5061YRJZ-1500RL7 −40°C to +125°C AD5061YRJZ-1REEL7 −40°C to +125°C EVAL-AD5061EBZ RoHS Compliant Part. ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...

Related keywords