AD5061 Analog Devices, AD5061 Datasheet - Page 7

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AD5061

Manufacturer Part Number
AD5061
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD5061

Resolution (bits)
16bit
Dac Update Rate
1.3MSPS
Dac Settling Time
4µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
Ser,SPI

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
DIN
V
V
V
AGND
DACGND
SYNC
SCLK
DD
REF
OUT
Description
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and V
Reference Voltage Input.
Analog Output Voltage from DAC.
Ground Input to the DAC.
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
Ground Reference Point for Analog Circuitry.
V
V
V
DIN
OUT
REF
DD
Figure 3. Pin Configuration
4
1
2
3
Rev. B | Page 7 of 20
(Not to Scale)
AD5061
TOP VIEW
8
7
6
5
SCLK
SYNC
DACGND
AGND
DD
should be decoupled to GND.
AD5061

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