AD5061 Analog Devices, AD5061 Datasheet - Page 15

• Manufacturer Part Number: AD5061
• Manufacturer: Analog Devices

Specifications of AD5061

• Resolution (bits): 16bit
• Dac Update Rate: 1.3MSPS
• Dac Settling Time: 4µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

THEORY OF OPERATION
The AD5061 is a single 16-bit, serial input, voltage output DAC.
It operates from supply voltages of 2.7 V to 5.5 V. Data is writ-
ten to the AD5061 in a 24-bit word format, via a 3-wire serial
interface.
The AD5061 incorporates a power-on reset circuit that ensures
the DAC output powers up to zero-scale or midscale. The
device also has a software power-down mode pin that reduces
the typical current consumption to less than 1 μA.
DAC ARCHITECTURE
The DAC architecture of the AD5061 consists of two matched
DAC sections. A simplified circuit diagram is shown in
Figure 37. The four MSBs of the 16-bit data word are decoded
to drive 15 switches, E1 to E15. Each of these switches connects
one of 15 matched resistors to either DACGND or V
output.
S0 to S11 of a 12-bit voltage mode R-2R ladder network.
V
REFERENCE BUFFER
The AD5061 operates with an external reference. The reference
input (V
input voltage is then used to provide a buffered reference for the
DAC core.
SERIAL INTERFACE
The AD5061 has a 3-wire serial interface ( SYNC , SCLK, and
DIN), which is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs. See
timing diagram of a typical write sequence.
REF
0
The remaining 12 bits of the data word drive switches
0
2R
REF
) has an input range of 2 V to V
12-BIT R-2R LADDER
2R
S0
0
Figure 37. DAC Ladder Structure
0
2R
S1
0
S11
2R
0
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
PD1
2R
E1
PD0
DD
2R
E2
− 50 mV. This
Figure 2
DB15 (MSB)
D15
0
0
1
1
2R
E15
0
1
0
1
REF
D14
for a
Figure 38. Input Register Contents
buffer
NORMAL OPERATION
3-STATE
100kΩ TO GND
1kΩ TO GND
V
OUT
D13
Rev. B | Page 15 of 20
D12
D11
POWER-DOWN MODES
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making these parts compatible with high speed
DSPs. On the 24th falling clock edge, the last data bit is clocked
in and the programmed function is executed (that is, a change
in the DAC register contents and/or a change in the mode of
operation).
At this stage, the SYNC line may be kept low or be brought
high. In either case, it must be brought high for a minimum of
12 ns before the next write sequence so that a falling edge of
SYNC can initiate the next write sequence. Because the SYNC
buffer draws more current when V
V
for an even lower power operation of the part. As previously
indicated, however, it must be brought high again just before
the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide; see Figure 38. PD1 and
PD0 are control bits that control which mode of operation the
part is in (normal mode or any one of three power-down
modes). There is a more complete description of the various
modes in the Power-Down Modes section. The next 16 bits are
the data bits. These are transferred to the DAC register on the
24th falling edge of SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 24 falling edges of SCLK and the DAC is updated on the
24th falling edge. However, if SYNC is brought high before the
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs; see
IH
D10
= 0.8 V, SYNC should be idled low between write sequences
D9
DATA BITS
D8
D7
D6
D5
IH
D4
= 1.8 V than it does when
D3
Figure 41
D2
.
AD5061
D1
DB0 (LSB)
D0