ADUC834 Analog Devices, ADUC834 Datasheet - Page 15

• Manufacturer Part Number: ADUC834
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 62kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC834

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 4
• Other: PWM

Stack Pointer (SP and SPH)
The SP SFR is the stack pointer and is used to hold an internal
RAM address that is called the ‘top of the stack.’ The SP Register
is incremented before data is stored during PUSH and CALL
executions. While the Stack may reside anywhere in on-chip
RAM, the SP Register is initialized to 07H after a reset. This
causes the stack to begin at location 08H.
As mentioned earlier, the ADuC834 offers an extended 11-bit
stack pointer. The three extra bits to make up the 11-bit stack
pointer are the 3 LSBs of the SPH byte located at B7H.
Program Status Word (PSW)
The PSW SFR contains several bits reflecting the current status
of the CPU as detailed in Table I.
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
Power Control SFR (PCON)
The PCON SFR contains bits for power-saving options and
general-purpose status flags as shown in Table II.
The TIC (wake-up/RTC timer) can be used to accurately wake up
the ADuC834 from power-down at regular intervals. To use the
TIC to wake up the ADuC834 from power-down, the OSC_PD
bit in the PLLCON SFR must be clear and the TIC must be
enabled.
SFR Address
Power-On Default Value
Bit Addressable
REV. A
Table I. PSW SFR Bit Designations
Name
CY
AC
F0
RS1
RS0
OV
F1
P
Description
Carry Flag
Auxiliary Carry Flag
General-Purpose Flag
Register Bank Select Bits
RS1
0
0
1
1
Overflow Flag
General-Purpose Flag
Parity Bit
D0H
No
00H
Yes
87H
00H
RS0
0
1
0
1
Selected Bank
0
1
2
3
–15–
Bit
7
6
5
4
3
2
1
0
ADuC834 CONFIGURATION SFR (CFG834)
The CFG834 SFR contains the necessary bits to configure the
internal XRAM and the extended SP. By default it configures
the user into 8051 mode, i.e., extended SP is disabled, internal
XRAM is disabled.
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
Name
SMOD
SERIPD
INT0PD
ALEOFF
GF1
GF0
PD
IDL
Name
EXSP
–––
–––
–––
–––
–––
–––
XRAMEN
Table III. CFG834 SFR Bit Designations
Table II. PCON SFR Bit Designations
Description
Extended SP Enable. If this bit is set, the
stack will roll over from SPH/SP = 00FFH
to 0100H. If this bit is clear, the SPH SFR
will be disabled and the stack will roll
over from SP = FFH to SP = 00H
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
XRAM Enable Bit. If this bit is set, the
internal XRAM will be mapped into the
lower 2 Kbytes of the external address
space. If this bit is clear, the internal
XRAM will not be accessible and the
external data memory will be mapped
into the lower 2 Kbytes of external data
memory. (See Figure 3.)
Description
Double UART Baud Rate
SPI Power-Down Interrupt Enable
INT0 Power-Down Interrupt Enable
Disable ALE Output
General-Purpose Flag Bit
General-Purpose Flag Bit
Power-Down Mode Enable
Idle Mode Enable
AFH
00H
No
ADuC834