ADUC834 Analog Devices, ADUC834 Datasheet - Page 34

• Manufacturer Part Number: ADUC834
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 62kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC834

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 4
• Other: PWM

Using the D/A Converter
The on-chip D/A converter architecture consists of a resistor
string DAC followed by an output buffer amplifier, the func-
tional equivalent of which is illustrated in Figure 21.
ADuC834
DAC
The ADuC834 incorporates a 12-bit, voltage output DAC
on-chip. It has a rail-to-rail voltage output buffer capable of driving
10 kΩ/100 pF. It has two selectable ranges, 0 V to V
nal bandgap 2.5 V reference) and 0 V to AV
12-bit or 8-bit mode. The DAC has a control register, DACCON,
and two data registers, DACH/L. The DAC output can be
Bit
7
6
5
4
3
2
1
0
DACH/L
Function
SFR Address
Power-On Default Value
Bit Addressable
Figure 21. Resistor String DAC Functional Equivalent
AV
V
REF
DD
Name
–––
–––
–––
DACPIN
DAC8
DACRN
DACCLR
DACEN
R
R
R
R
R
ADuC834
DAC Data Registers
DAC Data Registers, written by user to update the DAC output.
DACL (DAC Data Low Byte)
DACH (DAC Data High Byte)
00H
No
(FROM MCU)
DISABLE
OUTPUT
BUFFER
HIGH-Z
Description
Reserved for Future Use
Reserved for Future Use
Reserved for Future Use
DAC Output Pin Select.
Set by the user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC).
Cleared by user to direct the DAC output to Pin 3 (P1.2/DAC/IEXC1).
DAC 8-bit Mode Bit.
Set by user to enable 8-bit DAC operation. In this mode, the 8-bits in DACL SFR are routed
to the 8 MSBs of the DAC, and the 4 LSBs of the DAC are set to zero.
Cleared by user to operate the DAC in its normal 12-bit mode of operation.
DAC Output Range Bit.
Set by user to configure DAC range of 0–AV
Cleared by user to configure DAC range of 0 V–2.5 V (V
DAC Clear Bit.
Set to 1 by user to enable normal DAC operation.
Cleared to 0 by user to reset DAC data registers DACL/H to zero.
DAC Enable Bit.
Set to 1 by user to enable normal DAC operation.
Cleared to 0 by user to power down the DAC.
DD
Table XV. DACCON SFR Bit Designations
. It can operate in
12
DAC
REF
(the inter-
–34–
FBH
FCH
Both Registers
Both Registers
programmed to appear at Pin 3 or Pin 12. It should be noted
that in 12-bit mode, the DAC voltage output will be updated as
soon as the DACL data SFR has been written; therefore, the
DAC data registers should be updated as DACH first, followed
by DACL. The 12-bit DAC data should be written into DACH/L
right-justified such that DACL contains the lower eight bits,
and the lower nibble of DACH contains the upper four bits.
Features of this architecture include inherent guaranteed mono-
tonicity and excellent differential linearity. As illustrated in
Figure 21, the reference source for the DAC is user selectable in
software. It can be either AV
the DAC output transfer function spans from 0 V to the voltage
at the AV
function spans from 0 V to the internal V
output buffer amplifier features a true rail-to-rail output stage
implementation. This means that, unloaded, each output is
capable of swinging to within less than 100 mV of both AV
and ground. Moreover, the DAC’s linearity specification (when
driving a 10 kΩ resistive load to ground) is guaranteed through
the full transfer function except codes 0 to 48 in 0-to-V
mode and 0 to 100 and 3950 to 4095 in 0-to-V
Linearity degradation near ground and V
of the output amplifier, and a general representation of its effects
(neglecting offset and gain error) is illustrated in Figure 22. The
dotted line in Figure 22 indicates the ideal transfer function, and
the solid line represents what the transfer function might look
like with endpoint nonlinearities due to saturation of the output
amplifier.
DD
DD
pin. In 0-to-V
.
REF
REF
).
DD
mode, the DAC output transfer
or V
REF
DD
. In 0-to-AV
REF
is caused by saturation
(2.5 V). The DAC
DD
mode.
DD
mode,
REF
REV. A
DD