ADUC834 Analog Devices, ADUC834 Datasheet - Page 29

• Manufacturer Part Number: ADUC834
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 62kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC834

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 4
• Other: PWM

Like EEPROM, Flash memory can be programmed in-system at
a byte level, although it must first be erased; the erase being
performed in page blocks. Thus, Flash memory is often and
more correctly referred to as Flash/EE memory.
Overall, Flash/EE memory represents a step closer to the ideal
memory device that includes nonvolatility, in-circuit program-
mability, high density, and low cost. Incorporated in the
ADuC834, Flash/EE memory technology allows the user to
update program code space in-circuit, without the need to replace
onetime programmable (OTP) devices at remote operating nodes.
Flash/EE Memory and the ADuC834
The ADuC834 provides two arrays of Flash/EE memory for
user applications. 62 Kbytes of Flash/EE Program space are
provided on-chip to facilitate code execution without any exter-
nal discrete ROM device requirements. The program memory
can be programmed in-circuit, using the serial download mode
provided, using conventional third party memory programmers,
or via any user defined protocol in User Download (ULOAD) Mode.
A 4 Kbyte Flash/EE Data Memory space is also provided on-chip.
This may be used as a general-purpose, nonvolatile scratchpad
area. User access to this area is via a group of seven SFRs. This
space can be programmed at a byte level, although it must first
be erased in 4-byte pages.
ADuC834 Flash/EE Memory Reliability
The Flash/EE Program and Data Memory arrays on the ADuC834
are fully qualified for two key Flash/EE memory characteristics,
namely Flash/EE Memory Cycling Endurance and Flash/EE
Memory Data Retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many Program, Read, and Erase cycles. In real
terms, a single endurance cycle is composed of four independent,
sequential events. These events are defined as:
REV. A
a. initial page erase sequence
b. read/verify sequence
c. byte program sequence
d. second read/verify sequence
SPACE EFFICIENT/
Figure 15. Flash/EE Memory Development
DENSITY
TECHNOLOGY
EPROM
FLASH/EE MEMORY
TECHNOLOGY
TECHNOLOGY
A single Flash/EE
Memory Endurance
Cycle
EEPROM
REPROGRAMMABLE
IN-CIRCUIT
–29–
In reliability qualification, every byte in both the program and
data Flash/EE memory is cycled from 00H to FFH until a first
fail is recorded, signifying the endurance limit of the on-chip
Flash/EE memory.
As indicated in the specification pages of this data sheet, the
ADuC834 Flash/EE memory endurance qualification has been
carried out in accordance with JEDEC Specification A117 over
the industrial temperature range of –40°C, +25°C, +85°C, and
+125°C. The results allow the specification of a minimum
endurance figure over supply and temperature of 100,000
cycles, with an endurance figure of 700,000 cycles being typical
of operation at 25°C.
Retention quantifies the ability of the Flash/EE memory to retain
its programmed data over time. Again, the ADuC834 has been
qualified in accordance with the formal JEDEC Retention Life-
time Specification (A117) at a specific junction temperature
(T
Flash/EE memory is cycled to its specified endurance limit
described above, before data retention is characterized. This
means that the Flash/EE memory is guaranteed to retain its data
for its full specified retention lifetime every time the Flash/EE
memory is reprogrammed. It should also be noted that retention
lifetime, based on an activation energy of 0.6 eV, will derate
with T
J
= 55°C). As part of this qualification procedure, the
J
300
250
200
150
100
as shown in Figure 16.
Figure 16. Flash/EE Memory Data Retention
50
0
40
50
T
J
60
JUNCTION TEMPERATURE – C
ADI SPECIFICATION
100 YEARS MIN.
AT T
70
J
= 55 C
80
90
ADuC834
100
110