LPC1114FBD48 NXP Semiconductors, LPC1114FBD48 Datasheet - Page 23

• Manufacturer Part Number: LPC1114FBD48
• Description: The LPC1114FBD48 is an ARM Cortex-M0 microcontroller and it can operate up to 50 MHz
• Manufacturer: NXP Semiconductors

NXP Semiconductors
[1]
[2]
[3]
[4]
[5]
[6]
Table 9.
LPC111X
Product data sheet
Symbol
PIO0_0 to PIO0_11
RESET/PIO0_0
PIO0_1/CLKOUT/
CT32B0_MAT2
PIO0_2/SSEL0/
CT16B0_CAP0
PIO0_3
PIO0_4/SCL
PIO0_5/SDA
PIO0_6/SCK0
PIO0_7/CTS
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V
no pull-up/down enabled.
See
reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down
mode.
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see
I
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
2
C-bus pads compliant with the I
Figure 46
LPC1100 and LPC1100L series: LPC1113/14 pin description table (LQFP48 package)
for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to
Pin
3
4
10
14
15
16
22
23
[2]
[3]
[3]
[3]
[4]
[4]
[3]
[3]
Start
logic
input
yes
yes
yes
yes
yes
yes
yes
yes
2
C-bus specification for I
Type
I
I/O
I/O
O
O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 1 March 2012
Reset
state
[1]
I; PU
-
I; PU
-
-
I; PU
-
-
I; PU
I; IA
-
I; IA
-
I; PU
-
I; PU
-
2
C standard mode and I
Description
Port 0 — Port 0 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 0 pins
depends on the function selected through the IOCONFIG
register block.
RESET — External reset input with 20 ns glitch filter. A
LOW-going pulse as short as 50 ns on this pin resets the
device, causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0.
PIO0_0 — General purpose digital input/output pin with 10 ns
glitch filter.
PIO0_1 — General purpose digital input/output pin. A LOW
level on this pin during reset starts the ISP command handler.
CLKOUT — Clockout pin.
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2 — General purpose digital input/output pin.
SSEL0 — Slave Select for SPI0.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 — General purpose digital input/output pin.
PIO0_4 — General purpose digital input/output pin
(open-drain).
SCL — I
sink only if I
configuration register.
PIO0_5 — General purpose digital input/output pin
(open-drain).
SDA — I
only if I
register.
PIO0_6 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
PIO0_7 — General purpose digital input/output pin
(high-current output driver).
CTS — Clear To Send input for UART.
2
C Fast-mode Plus is selected in the I/O configuration
2
2
LPC1110/11/12/13/14/15
C-bus, open-drain clock input/output. High-current
C-bus, open-drain data input/output. High-current sink
2
C Fast-mode Plus is selected in the I/O
2
C Fast-mode Plus.
32-bit ARM Cortex-M0 microcontroller
Figure
DD
© NXP B.V. 2012. All rights reserved.
45).
level ); IA = inactive,
Figure
23 of 103
45).