LPC11C12FBD48 NXP Semiconductors, LPC11C12FBD48 Datasheet - Page 32

The LPC11C12FBD48 is an ARM Cortex-M0 microcontroller designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit arch

LPC11C12FBD48

Manufacturer Part Number
LPC11C12FBD48
Description
The LPC11C12FBD48 is an ARM Cortex-M0 microcontroller designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit arch
Manufacturer
NXP Semiconductors
Datasheet

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[13] 3-state outputs go into 3-state mode in Deep power-down mode.
[14] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[15] To V
Table 7.
T
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
LPC11CX2_CX4
Product data sheet
Symbol
V
C
E
E
E
E
E
R
R
amb
IA
D
L(adj)
O
G
T
ia
vsi
i
The ADC is monotonic, there are no missing codes.
The differential linearity error (E
The integral non-linearity (E
appropriate adjustment of gain and offset errors. See
The offset error (E
ideal curve. See
The gain error (E
error, and the straight line which fits the ideal transfer curve. See
The absolute error (E
ADC and the ideal transfer curve. See
T
Input resistance R
=
amb
SS
40
= 25 C; maximum sampling frequency f
.
ADC static characteristics
C to +85
Parameter
analog input voltage
analog input capacitance
differential linearity error
integral non-linearity
offset error
gain error
absolute error
voltage source interface
resistance
input resistance
9.1 ADC characteristics
Figure
G
i
O
) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
depends on the sampling frequency fs: R
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
C unless otherwise specified; ADC frequency 4.5 MHz, V
T
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
6.
L(adj)
D
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
) is the difference between the actual step width and the ideal step width. See
Figure
All information provided in this document is subject to legal disclaimers.
Conditions
s
6.
= 400 kSamples/s and analog input capacitance C
Rev. 3 — 27 June 2011
Figure
i
6.
= 1 / (f
Figure
s
 C
6.
ia
).
[1][2]
[7][8]
[3]
[4]
[5]
[6]
Min
0
-
-
-
-
-
-
-
-
32-bit ARM Cortex-M0 microcontroller
DD
= 2.5 V to 3.6 V.
LPC11Cx2/Cx4
Typ
-
-
-
-
-
-
-
-
-
ia
= 1 pF.
Max
V
1
 1
 1.5
 3.5
0.6
 4
40
2.5
Figure
© NXP B.V. 2011. All rights reserved.
DD
6.
Unit
V
pF
LSB
LSB
LSB
%
LSB
k
M
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