LPC11C12FBD48 NXP Semiconductors, LPC11C12FBD48 Datasheet - Page 7

• Manufacturer Part Number: LPC11C12FBD48
• Description: The LPC11C12FBD48 is an ARM Cortex-M0 microcontroller designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit arch
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 3.
LPC11CX2_CX4
Product data sheet
Symbol
PIO0_0 to PIO0_11
RESET/PIO0_0
PIO0_1/CLKOUT/
CT32B0_MAT2
PIO0_2/SSEL0/
CT16B0_CAP0
PIO0_3
PIO0_4/SCL
PIO0_5/SDA
PIO0_6/SCK0
PIO0_7/CTS
PIO0_8/MISO0/
CT16B0_MAT0
PIO0_9/MOSI0/
CT16B0_MAT1
SWCLK/PIO0_10/
SCK0/
CT16B0_MAT2
LPC11C12/C14 pin description table
6.2 Pin description
Pin
3
4
10
14
15
16
22
23
27
28
29
[2]
[3]
[3]
[3]
[4]
[4]
[3]
[3]
[3]
[3]
[3]
Start
logic
inputs
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Type
I
I/O
I/O
O
O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
O
I/O
I/O
O
I
I/O
I/O
O
All information provided in this document is subject to legal disclaimers.
Reset
state
[1]
I; PU
-
I; PU
-
-
I; PU
-
-
I; PU
I; IA
-
I; IA
-
I; PU
-
I; PU
-
I; PU
-
-
I; PU
-
-
I; PU
-
-
-
Rev. 3 — 27 June 2011
Description
Port 0 — Port 0 is a 12-bit I/O port with individual direction and
function controls for each bit. The operation of port 0 pins depends
on the function selected through the IOCONFIG register block.
RESET — External reset input with 20 ns glitch filter. A LOW-going
pulse as short as 50 ns on this pin resets the device, causing I/O
ports and peripherals to take on their default states, and processor
execution to begin at address 0.
PIO0_0 — General purpose digital input/output pin with 10 ns glitch
filter.
PIO0_1 — General purpose digital input/output pin. A LOW level on
this pin during reset starts the flash ISP command handler via UART
(if PIO0_3 is HIGH) or via C_CAN (if PIO0_3 is LOW).
CLKOUT — Clockout pin.
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2 — General purpose digital input/output pin.
SSEL0 — Slave Select for SPI0.
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_3 — General purpose digital input/output pin. This pin is
monitored during reset: Together with a LOW level on pin PIO0_1, a
LOW level starts the flash ISP command handler via C_CAN and a
HIGH level starts the flash ISP command handler via UART.
PIO0_4 — General purpose digital input/output pin (open-drain).
SCL — I
if I
PIO0_5 — General purpose digital input/output pin (open-drain).
SDA — I
if I
PIO0_6 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
PIO0_7 — General purpose digital input/output pin (high-current
output driver).
CTS — Clear To Send input for UART.
PIO0_8 — General purpose digital input/output pin.
MISO0 — Master In Slave Out for SPI0.
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
PIO0_9 — General purpose digital input/output pin.
MOSI0 — Master Out Slave In for SPI0.
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
SWCLK — Serial wire clock.
PIO0_10 — General purpose digital input/output pin.
SCK0 — Serial clock for SPI0.
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
2
2
C Fast-mode Plus is selected in the I/O configuration register.
C Fast-mode Plus is selected in the I/O configuration register.
2
2
C-bus, open-drain clock input/output. High-current sink only
C-bus, open-drain data input/output. High-current sink only
32-bit ARM Cortex-M0 microcontroller
LPC11Cx2/Cx4
© NXP B.V. 2011. All rights reserved.
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