LPC11C12FBD48 NXP Semiconductors, LPC11C12FBD48 Datasheet - Page 48

• Manufacturer Part Number: LPC11C12FBD48
• Description: The LPC11C12FBD48 is an ARM Cortex-M0 microcontroller designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit arch
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 18.
[1]
[2]
[3]
[4]
LPC11CX2_CX4
Product data sheet
Symbol
t
t
t
t
DS
DH
v(Q)
h(Q)
T
main clock frequency f
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
T
T
T
cy(clk)
amb
cy(clk)
amb
= 40 C to 85 C.
= 25 C; for normal voltage supply range: V
= (SSPCLKDIV  (1 + SCR)  CPSDVSR) / f
= 12  T
Dynamic characteristics of SPI pins in SPI mode
Parameter
data set-up time
data hold time
data output valid time in SPI mode
data output hold time in SPI mode
cy(PCLK)
main
.
Fig 21. SPI master timing in SPI mode
, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
SCK (CPOL = 0)
SCK (CPOL = 1)
Conditions
in SPI mode
in SPI mode
Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.
MOSI
MISO
MOSI
MISO
All information provided in this document is subject to legal disclaimers.
DD
main
= 3.3 V.
DATA VALID
Rev. 3 — 27 June 2011
DATA VALID
. The clock cycle time derived from the SPI bit rate T
t
v(Q)
[3][4]
[3][4]
[3][4]
[3][4]
DATA VALID
T
DATA VALID
cy(clk)
Min
0
3  T
-
-
t
v(Q)
t
DS
DATA VALID
cy(PCLK)
DATA VALID
t
clk(H)
t
t
DH
DS
32-bit ARM Cortex-M0 microcontroller
+ 4
DATA VALID
DATA VALID
Typ
-
-
-
-
t
clk(L)
t
DH
LPC11Cx2/Cx4
t
h(Q)
Max
-
-
3  T
2  T
t
cy(PCLK)
cy(PCLK)
h(Q)
cy(clk)
© NXP B.V. 2011. All rights reserved.
is a function of the
+ 11
+ 5
CPHA = 1
CPHA = 0
002aae829
48 of 62
ns
Unit
ns
ns
ns