LPC2290 NXP Semiconductors, LPC2290 Datasheet
LPC2290
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LPC2290 Summary of contents
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... The LPC2290 provides GPIOs depending on bus configuration. With a wide range of additional serial communications interfaces also suited for communication gateways and protocol converters as well as many other general-purpose applications. ...
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... I/O power supply range of 3 3 Ordering information Table 1. Type number LPC2290FBD144 LPC2290FBD144/01 3.1 Ordering options Table 2. Type number LPC2290FBD144 LPC2290FBD144/ LPC2290_3 Product data sheet 16/32-bit ARM microcontroller with external memory interface Ordering information Package Name Description LQFP144 plastic low profile quad flat package; ...
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... P1[31:16], P1[1:0] PURPOSE I/O P2[31:0] P3[31:0] PWM6 to PWM1 REAL-TIME CLOCK (1) When test/debug interface is used, GPIO/other functions sharing these pins are not available. (2) Pins shared with GPIO. (3) Available in LPC2290/01 only. Fig 1. Block diagram LPC2290_3 Product data sheet 16/32-bit ARM microcontroller with external memory interface (1) (1) TMS TDI ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. LQFP144 pinning LPC2290_3 Product data sheet 16/32-bit ARM microcontroller with external memory interface 1 108 LPC2290 36 73 002aaa797 Rev. 03 — 16 November 2006 LPC2290 © NXP B.V. 2006. All rights reserved ...
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... PWM2 — Pulse Width Modulator output 2. I EINT2 — External interrupt 2 input. I/O P0.8 — General purpose digital input/output pin. O TXD1 — Transmitter output for UART1. O PWM4 — Pulse Width Modulator output 4. Rev. 03 — 16 November 2006 LPC2290 2 C-bus 2 C-bus © NXP B.V. 2006. All rights reserved ...
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... P0.18 — General purpose digital input/output pin. I CAP1.3 — Capture input for Timer 1, channel 3. I/O MISO1 — Master In Slave Out for SPI1/SSP. Data input to SPI master or data output from SPI slave (SSP is available in LPC2290/01 only). O MAT1.3 — Match output for Timer 1, channel 3. Rev. 03 — 16 November 2006 LPC2290 © ...
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... P0.19 — General purpose digital input/output pin. O MAT1.2 — Match output for Timer 1, channel 2. I/O MOSI1 — Master Out Slave In for SPI1/SSP. Data output from SPI master or data input to SPI slave (SSP is available in LPC2290/01 only). I CAP1.2 — Capture input for Timer 1, channel 2. I/O P0.20 — General purpose digital input/output pin. ...
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... TDI — Test Data in for JTAG interface. I/O P1.29 — General purpose digital input/output pin. I TCK — Test Clock for JTAG interface. I/O P1.30 — General purpose digital input/output pin. I TMS — Test Mode Select for JTAG interface. Rev. 03 — 16 November 2006 LPC2290 © NXP B.V. 2006. All rights reserved ...
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... D15 — External memory data line 15. I/O P2.16 — General purpose digital input/output pin. I/O D16 — External memory data line 16. I/O P2.17 — General purpose digital input/output pin. I/O D17 — External memory data line 17. Rev. 03 — 16 November 2006 LPC2290 © NXP B.V. 2006. All rights reserved ...
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... Port 3 — Port 32-bit bidirectional I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the Pin Connect Block. Rev. 03 — 16 November 2006 LPC2290 © NXP B.V. 2006. All rights reserved ...
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... A17 — External memory address line 17. I/O P3.18 — General purpose digital input/output pin. O A18 — External memory address line 18. I/O P3.19 — General purpose digital input/output pin. O A19 — External memory address line 19. Rev. 03 — 16 November 2006 LPC2290 © NXP B.V. 2006. All rights reserved ...
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... Input to the oscillator circuit and internal clock generator circuits. O Output from the oscillator amplifier. I Ground reference. I Analog ground reference. This should nominally be the same voltage but should be isolated to minimize noise and error. SS Rev. 03 — 16 November 2006 LPC2290 © NXP B.V. 2006. All rights reserved ...
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... Analog 3.3 V pad power supply: This should be nominally the same voltage as V but should be isolated to minimize noise and error. DD(3V3) 2 C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output Rev. 03 — 16 November 2006 LPC2290 but DD(1V8) © NXP B.V. 2006. All rights reserved ...
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... ARM processor connected to a 16-bit memory system. 6.2 On-chip SRAM On-chip SRAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. The LPC2290 provides SRAM and the LPC2290/01 provides SRAM. 6.3 Memory map ...
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... NXP Semiconductors Fig 3. LPC2290 and LPC2290/01 memory map 6.4 Interrupt controller The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... RX Line Status (RLS) Transmit Holding Register empty (THRE) RX Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) Auto-Baud Time-Out (ABTO) (available in LPC2290/01 only) End of Auto-Baud (ABEO) Match (MR0, MR1, MR2, MR3, MR4, MR5, MR6) SI (state change) SPIF, MODF Rev. 03 — ...
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... ARM microcontroller with external memory interface Interrupt sources …continued Flag(s) Source: SPI1 SPI Interrupt Flag (SPIF), Mode Fault (MODF) 11 Source: SSP (available in LPC2290/01 only) TX FIFO at least half empty (TXRIS) RX FIFO at least half full (RXRIS) Receive Timeout condition (RTRIS) Receive Overrun (RORRIS) ...
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... Acceptance Filter can provide FullCAN-style automatic reception for selected Standard identifiers. • Full CAN messages can generate interrupts. 6.10 UARTs The LPC2290 contains two UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface. 6.10.1 Features • Receive and Transmit FIFOs. ...
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... The I 6.12 SPI serial I/O controller The LPC2290 contains two SPIs. The SPI is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master ...
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... Often only one of these data flows carries meaningful data. The SSP and SPI1 share the same pins on LPC2290/01. After a reset, SPI1 is enabled and SSP is disabled. 6.13.1 Features • ...
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... Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. 6.14.2 Timer features available in LPC2290/01 only • Timers can count cycles of the externally supplied clock providing external event counting functionality 6.15 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘ ...
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... Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2290. The Timer is designed to count cycles of the peripheral clock (PCLK) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is also based on match register events ...
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... PLL settling time is 100 s. 6.18.3 Reset and wake-up timer Reset has two sources on the LPC2290: the RESET pin and watchdog reset. The RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the Wake-up Timer (see Wake-up Timer description below), causing the internal chip reset to remain asserted until the external reset is de-asserted, the oscillator is running, a fi ...
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... External interrupt inputs The LPC2290 include up to nine edge or level sensitive External Interrupt Inputs as selectable pin functions. When the pins are combined, external events can be processed as four independent interrupt signals. The External Interrupt Inputs can optionally be used to wake up the processor from Power-down mode ...
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... EmbeddedICE logic. 6.19.2 Embedded trace Since the LPC2290 has significant amounts of on-chip memory not possible to determine how the processor core is operating simply by observing the external pins. The Embedded Trace Macrocell (ETM) provides real-time trace capability for deeply embedded processor cores ...
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... ARM microcontroller with external memory interface [1] Conditions internal rail external rail [2][ tolerant I/O pins [2][4] other I/O pins [5] per supply pin [5] per ground pin [6] based on package heat transfer, not device power consumption [7] human body model; all pins Rev. 03 — 16 November 2006 LPC2290 Min Max Unit 0.5 +2.5 V 0.5 +3.6 V 0.5 +4.6 V 0.5 +5.1 V 0.5 +6 ...
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... I V < V < DD(3V3 1.8 V, DD(1V8) CCLK = 60 MHz code amb while(1){} executed from flash, no active peripherals V = 1.8 V, DD(1V8 amb V = 1.8 V, DD(1V8 amb V = 1.8 V, DD(1V8 125 C amb Rev. 03 — 16 November 2006 LPC2290 [1] Min Typ Max 1.65 1.8 1.95 3.0 3.3 3.6 2.5 3.3 3 100 - - ...
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... V, maximum condition for V I [8] Applies to P1[25:16]. LPC2290_3 Product data sheet 16/32-bit ARM microcontroller with external memory interface …continued Conditions OLS DD(3V3 grounded. DD(3V3 Rev. 03 — 16 November 2006 LPC2290 [1] Min Typ Max 0. DD(3V3 0.3V - 0.5V - DD(3V3 ...
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... Figure 4. Figure Figure 4. Rev. 03 — 16 November 2006 Min Typ [1][2][3] [1][ [1][ [1][ [1][ LPC2290 Max Unit V V DDA LSB 2 LSB 3 LSB 0 LSB Figure 4. © NXP B.V. 2006. All rights reserved ...
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... ARM microcontroller with external memory interface (2) (5) (4) (3) 1 LSB (ideal (LSB ) IA ideal ). D ). Rev. 03 — 16 November 2006 (1) 1018 1019 1020 1021 1022 1023 V V DDA SSA 1 LSB = 1024 LPC2290 offset gain error error 1024 002aaa668 © NXP B.V. 2006. All rights reserved ...
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... PLL is used external clock frequency if on-chip bootloader is used for initial code download Rev. 03 — 16 November 2006 LPC2290 Min Typ Max ...
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... WST1)) + cy(CCLK) ( 20) [2][ 20) cy(CCLK cy(CCLK [ WST2) cy(CCLK) [ WST2) cy(CCLK) [ cy(CCLK) [ cy(CCLK) [ cy(CCLK) Rev. 03 — 16 November 2006 LPC2290 Typ Max - + ...
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... RAM cy CCLK – cy CCLK – CYC WRITE cy CCLK t cy CCLK + INIT cy CCLK – ROM cy CCLK LPC2290 Unit cy(CCLK WST 1 – WST 2 – WST 1 – – © NXP B.V. 2006. All rights reserved. ...
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... ARM microcontroller with external memory interface t CSLAV OELAV t CHOEL t CSLDV t AVCSL t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV Rev. 03 — 16 November 2006 LPC2290 t CSHOEH t h(D) t OEHANV t CHOEH 002aaa749 t WEHANV t BLSHANV t WEHDNV t BLSHDNV 002aaa750 © NXP B.V. 2006. All rights reserved ...
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... NXP Semiconductors V 0 0.2V 0.2V 0.45 V Fig 7. External clock timing 9.2 LPC2290 power consumption measurements 60 I current DD (mA Test conditions: code executed from on-chip RAM; all peripherals are enabled in PCONP register; PCLK = (1) 1.8 V core (typical) (2) 1.65 V core (typical) Fig 8. LPC2290 I ...
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... Test conditions: Idle mode entered executing code from on-chip RAM; all peripherals are enabled in PCONP register; CCLK PCLK = . 4 (1) 1.8 V core (typical) (2) 1.65 V core (typical) Fig 9. LPC2290 I idle measured at different frequencies (CCLK) and temperatures DD 500 I current 400 300 ...
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... 0.20 20.1 20.1 22.15 22.15 0.5 0.09 19.9 19.9 21.85 21.85 REFERENCES JEDEC JEITA MS-026 Rev. 03 — 16 November 2006 detail 0.75 1.4 1 0.2 0.08 0.08 0.45 1.1 EUROPEAN PROJECTION LPC2290 SOT486 ( 1.1 0 ISSUE DATE 00-03-14 03-02-20 © NXP B.V. 2006. All rights reserved ...
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... General Purpose Input/Output Phase-Locked Loop Pulse Width Modulator Random Access Memory Reduced Instruction Set Computer Serial Peripheral Interface Static Random Access Memory Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Rev. 03 — 16 November 2006 LPC2290 © NXP B.V. 2006. All rights reserved ...
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... The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • New features specific to the LPC2290/01 have been added throughout. LPC2290-02 20041223 LPC2290-01 20040209 ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 03 — 16 November 2006 LPC2290 © NXP B.V. 2006. All rights reserved ...
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... NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Enhancements introduced with LPC2290/01 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Key features common for LPC2290 and LPC2290/ Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . 14 6.1 Architectural overview 6.2 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 Memory map ...