PSMN8R0-30YL NXP Semiconductors, PSMN8R0-30YL Datasheet - Page 7

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology

PSMN8R0-30YL

Manufacturer Part Number
PSMN8R0-30YL
Description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
PSMN8R0-30YL
Product data sheet
Fig 9.
Fig 11. Sub-threshold drain current as a function of
(mΩ)
R
10
10
10
10
10
10
(A)
DSon
I
D
40
30
20
10
-1
-2
-3
-4
-5
-6
0
of drain current; typical values
gate-source voltage
Drain-source on-state resistance as a function
0
0
V
GS
(V) = 2.8
20
min
3.0
1
40
typ
2
3.5
60
V
All information provided in this document is subject to legal disclaimers.
4.5
10
GS
003aab271
003aaf426
I
D
max
(V)
(A)
80
3
Rev. 2 — 16 May 2011
N-channel 8.3 mΩ 30 V TrenchMOS logic level FET in LFPAK
Fig 10. Drain-source on-state resistance as a function
Fig 12. Gate-source threshold voltage as a function of
R
(mΩ)
V
DSon
GS(th)
(V)
50
40
30
20
10
0
3
2
1
0
-60
of gate-source voltage; typical values
junction temperature
0
4
0
PSMN8R0-30YL
8
max
typ
min
60
12
120
© NXP B.V. 2011. All rights reserved.
16
003aaf427
003aaf111
T
V
j
GS
(°C)
(V)
180
20
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