STM8S007C8 STMicroelectronics, STM8S007C8 Datasheet - Page 11

• Manufacturer Part Number: STM8S007C8
• Description: Value line, 24 MHz STM8S 8-bit MCU, 64 Kbytes Flash, true data EEPROM
• Manufacturer: STMicroelectronics

Specifications of STM8S007C8

• Max Fcpu: up to 24 MHz, 0 wait states @ fCPU≤ 16 MHz
• Program: 64 Kbytes Flash; data retention 20 years at 55 °C after 100 cycles
• Data: 128 bytes true data EEPROM; endurance 100 kcycles
• Ram: 6 Kbytes
• Advanced Control Timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization

STM8S007C8
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4.1
Product overview
The following section intends to give an overview of the basic features of the STM8S007xx
value line functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
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Addressing
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Instruction set
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Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching for most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
8-bit accumulator
24-bit program counter - 16-Mbyte linear memory space
16-bit stack pointer - access to a 64 K-level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
20 addressing modes
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
Stack pointer relative addressing mode for local variables and parameter passing
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
Doc ID 022171 Rev 2
Product overview
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