ST72561J6 STMicroelectronics, ST72561J6 Datasheet - Page 139
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ST72561J6
Manufacturer Part Number
ST72561J6
Description
8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, LINSCI(TM), ACTIVE CAN
Manufacturer
STMicroelectronics
Datasheet
1.ST72561R9.pdf
(265 pages)
Specifications of ST72561J6
Hdflash Endurance
100 cycles, data retention 40 years at 85°C
5 Power Saving Modes
Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow
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LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
Figure 81. SCI Block Diagram in LIN Slave Mode
TDO
RDI
SCIBRR
TIE
LIN SLAVE BAUD RATE GENERATOR
SCICR2
LPR7
f
CPU
f
CPU
INTERRUPT
AUTO SYNCHRONIZATION
LIN SLAVE BAUD RATE
TCIE
CONTROL
Transmit Data Register (TDR)
SCI
TRANSMIT
CONTROL
RIE
Transmit Shift Register
/ LDIV
Write
UNIT
ILIE
TE
RE
LPR0
/16
RWU
WAKE
UNIT
UP
R8
SBK
CONVENTIONAL BAUD RATE
EXTENDED PRESCALER
T8 SCID M
Received Data Register (RDR)
LDUM
GENERATOR
Read
Receive Shift Register
TDRE TC RDRF IDLE
+
LINE
WAKE
RECEIVER
CONTROL
LSLV
(DATA REGISTER) SCIDR
PCE
LASE
SCICR1
PS PIE
LHDM
OR/
LHE
0
1
TRANSMITTER
LHIE
RECEIVER
NF
CLOCK
CLOCK
LHDF
FE
SCICR3
SCISR
LSF
PE
ST72561
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